Topic: Custom RAM Timings for GPU's with GDDR5 - DOWNLOAD LINKS - UPDATED - page 61. (Read 155645 times)
February 03, 2017, 02:42:43 PM
February 03, 2017, 02:40:16 PM
We are curious about your results 
I didnt have time in the past few days to continue experimenting, but hopefuly at the weekend.
I didnt have time in the past few days to continue experimenting, but hopefuly at the weekend.
Only real test I've done so far is running eth+dcr under the regular 1500 straps then under the modded 1500 straps.
1101/1921/1500str => 27.03 eth
1101/1921/1500mod => 27.19 eth
Just a bit better.
February 03, 2017, 02:36:16 PM
January 30, 2017, 08:46:12 PM
tRFC @1500MHz Hynix strap is 148
Oops, you're right - those numbers do look wrong.
February 03, 2017, 02:02:16 PM
We are curious about your results
I didnt have time in the past few days to continue experimenting, but hopefuly at the weekend.
I didnt have time in the past few days to continue experimenting, but hopefuly at the weekend.
February 03, 2017, 01:29:16 PM
Code:
$ ./strap -c trc:60 -c trcdw:13 -c trcdwa:13 -c trrd:5 -c tcl:20 -c tr2w:28 -c tw2r:15 -c trfc:145 -c trprda:11 -c trpwra:46
REGISTER KEY VALUE NEWVALUE
RAS trc 61 60
RAS trcdr 20 20
RAS trcdra 20 20
RAS trcdw 14 13
RAS trcdwa 14 13
RAS trrd 6 5
RAS unused1 0 0
CAS tcl 18 20
CAS tnopr 0 0
CAS tnopw 0 0
CAS tr2r 5 5
CAS tr2w 25 28
CAS tw2r 17 15
CAS unused1 2 2
CAS unused2 0 0
CAS unused3 0 0
MISC trfc 148 145
MISC trp 9 9
MISC trprda 11 11
MISC trpwra 48 46
MISC unused1 0 0
MISC unused2 1 1
MISC unused3 0 0
Old Strap => 777000000000000022339D00CE516A3D9055111230CB4409004AE600740114206A8900A002003120150F292F94273116
New Strap => 777000000000000022339D00AD515A3CC0550F142ECB1409004AE600740114206A8900A002003120150F292F94273116
What could possibly go wrong!
January 30, 2017, 05:47:13 PM
Still wrong, but not entirely your fault - the documentation you're looking at is outdated.
Surely the 4.9 kernel has the correct offsets?
#define MC_SEQ_MISC_TIMING__TRP_WRA__SHIFT 0x0
#define MC_SEQ_MISC_TIMING__TRP_RDA__SHIFT 0x8
#define MC_SEQ_MISC_TIMING__TRP__SHIFT 0xf
#define MC_SEQ_MISC_TIMING__TRFC__SHIFT 0x14
You don't see TCKE there, do you?
Right, but that doesnt effect the offsets for MC_SEQ_MISC_TIMING as its the last 4 bits in the 32 bit index. So if 0x1c is unused, the fact that TCKE shows ZERO's in my table above agrees with that.
Now you get it.
February 03, 2017, 11:49:42 AM
Anyone who is wondering what the hell is happening here.. start by reading this
http://www.masterslair.com/memory-ram-timings-latency-cas-ras-tcl-trcd-trp-tras
http://www.tweakers.fr/timings.html
http://www.masterslair.com/memory-ram-timings-latency-cas-ras-tcl-trcd-trp-tras
http://www.tweakers.fr/timings.html
February 01, 2017, 05:20:03 AM
Share please good straps for 290x elpida bbbg. On zec have 337 H/s, 1050/1500 mHz.
January 30, 2017, 03:40:10 PM
Still wrong, but not entirely your fault - the documentation you're looking at is outdated.
Surely the 4.9 kernel has the correct offsets?
#define MC_SEQ_MISC_TIMING__TRP_WRA__SHIFT 0x0
#define MC_SEQ_MISC_TIMING__TRP_RDA__SHIFT 0x8
#define MC_SEQ_MISC_TIMING__TRP__SHIFT 0xf
#define MC_SEQ_MISC_TIMING__TRFC__SHIFT 0x14
You don't see TCKE there, do you?
January 31, 2017, 11:01:57 PM
your trp is still messed up.
sure enough
Code:
----------------------------------------------------------------------------------------------------
Strap (MISC) trfc trp trprda trpwra
----------------------------------------------------------------------------------------------------
MSI-470-Hynix-Stock-1125 111 7 9 40
MSI-470-Hynix-Stock-1250 123 8 10 44
MSI-470-Hynix-Stock-1375 136 9 10 46
MSI-470-Hynix-Stock-1425 141 9 11 47
MSI-470-Hynix-Stock-1500 148 9 11 48
MSI-470-Hynix-Stock-1625 164 11 12 55
MSI-470-Hynix-Stock-1750 173 11 13 57
MSI-470-Hynix-Stock-2000 197 13 15 62
----------------------------------------------------------------------------------------------------
January 31, 2017, 06:38:23 PM
your trp is still messed up.
January 30, 2017, 02:51:21 PM
January 31, 2017, 04:16:18 PM
Your right, the faster memory requires trfc's over 127, so they have to give more bits to accommodate it. That explains why tcke now finds itself in SEQ_PMG.
Code:
----------------------------------------------------------------------------------------------------
Strap (MISC) trfc trp trprda trpwra
----------------------------------------------------------------------------------------------------
MSI-470-Hynix-Stock-1125 111 3 9 40
MSI-470-Hynix-Stock-1250 123 4 10 44
MSI-470-Hynix-Stock-1375 136 4 10 46
MSI-470-Hynix-Stock-1425 141 4 11 47
MSI-470-Hynix-Stock-1500 148 4 11 48
MSI-470-Hynix-Stock-1625 164 5 12 55
MSI-470-Hynix-Stock-1750 173 5 13 57
MSI-470-Hynix-Stock-2000 197 6 15 62
----------------------------------------------------------------------------------------------------
January 31, 2017, 02:54:56 PM
Because it is not 7 bits?
This is from linux kernel.
Surely 0x1ff00000 gives 9 bits?
The way i see it, it should be decoded as (highter to lower bits):
If so then MISC_TIMING decodes from 1500 hynix strap as
I am more interested why unused2 contains data. Did i miss something?
This is from linux kernel.
Code:
#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x3f
#define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x0
#define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x3f00
#define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x8
#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0xf8000
#define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0xf
#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000
#define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x14
The way i see it, it should be decoded as (highter to lower bits):
Code:
Bits("unused3", 3), #Unused
Bits("TRFC", 9), #Auto-refresh command period - 1
Bits("TRP", 5), #Precharge command period - 1
Bits("unused2", 1), #Unused but defined as 1
Bits("TRP_RDA", 6), #From read with auto-precharge to active - 1
Bits("unused1", 2), #Unused
Bits("TRP_WRA", 6), #From write with auto-precharge to active - 1
Code:
unused3 = 0
TRFC = 148
TRP = 9
unused2 = 1
TRP_RDA = 11
unused1 = 0
TRP_WRA = 48
I am more interested why unused2 contains data. Did i miss something?
January 30, 2017, 01:18:59 PM
January 31, 2017, 02:14:30 PM
Be creative.
Thats the advantage of doing it in notepad by hand like me
Thats the advantage of doing it in notepad by hand like me
Oh... please show you work! I'd woud LOVE to see 148 come from 7 bits.
I never said that.
So then how do you explain a tRFC of 148
January 31, 2017, 02:02:04 PM
Be creative.
Thats the advantage of doing it in notepad by hand like me
Thats the advantage of doing it in notepad by hand like me
Oh... please show you work! I'd woud LOVE to see 148 come from 7 bits.
I never said that.
January 31, 2017, 12:01:23 PM
Be creative.
Thats the advantage of doing it in notepad by hand like me
Thats the advantage of doing it in notepad by hand like me
Oh... please show you work! I'd woud LOVE to see 148 come from 7 bits.
January 31, 2017, 11:12:22 AM
Be creative.
Thats the advantage of doing it in notepad by hand like me
Thats the advantage of doing it in notepad by hand like me
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