Topic: Custom RAM Timings for GPU&#039;s with GDDR5 - DOWNLOAD LINKS - UPDATED - page 62. (Read 155685 times)

Quote from: Wolf0 on January 25, 2017, 03:12:43 AM

Quote from: kilo17 on January 25, 2017, 02:52:43 AM

Quote from: kilo17 on January 21, 2017, 01:19:01 AM

Quote from: kilo17 on January 21, 2017, 12:41:33 AM

Quote from: Brewins on January 21, 2017, 12:24:56 AM

You guys are funny, I bet none of you have figured out all 20 of those timings. It is tough as shit to figure out- here's a challenge for you 3- if you kilo, jstefanop and eliovp can each post one of the following 3 timings from The Stilts Hyinx 1250 strap- I will then be a believer, otherwise I say you're all full of shit/

1 - tWR
2 - tWTR
3 - tRCDR

Good luck

- that's funny. I will do one- how about tWTR - it really doesn't matter to me

I changed my mind, I am going to post the tRTW to prevent giving away to much info - the tRTW in the following Stilt strap is 21

77 71 33 20 00 00 00 00 08 39 47 2A 50 55 0C 0B 24 20 45 04 00 46 C4 00 22 BB 1C 00 5C 0B 14 20 4A 89 00 A0 00 00 01 20 12 0C 21 1E 51 19 26 13

tRCDR - 0xE.

Correct me if I wrong, based on compare of custom straps from The Stilt with original one. Timing info contain in the string 77 71 33 20 00 00 00 00 08 39 47 2A and possible it's magic 3 registers one of them last or first is MC_SEQ_RAS_TIMING

MC_SEQ_RAS_TIMING is a bunch of timings, not just 1.

Ofc it's a 32 bit register where each value 4 bit. I've just want to know where exactly in this 48 byte strap this register. Also what about MC_SEQ_CAS_TIMING register, any interesting there?

Each value is not 4-bit, just some of them are.

SEQ_RAS [2 2 14 14 2 42] right?

That looks wrong, but I'm not certain. I DO know that the section posted is NOT MC_SEQ_RAS_TIMING, though. You missed it entirely.

dallase

member

Activity: 129

Merit: 10

dallase

member

Activity: 129

Merit: 10

Whatcha think?

Code:


$ ./multistrap2 
MSI-470-Hynix-Stock-1125 -> 777000000000000022FF1C006BBD572F40550F0D28C9F3060048C5004C0D14205A8900A000003120100C20246F1E2912
MSI-470-Hynix-Stock-1250 -> 777000000000000022FF1C008CC5583460550F0F2C4AB4070048C5005C0F14205A8900A000003120120D23287B222D13
MSI-470-Hynix-Stock-1375 -> 777000000000000022339D00CECD593980551111AE8A84080048C6006C0014206A8900A002003120140F262B88252F15
MSI-470-Hynix-Stock-1425 -> 777000000000000022339D00CE516A3B805511112FCBD408004AE6006C0014206A8900A002003120150F272D8D263015
MSI-470-Hynix-Stock-1500 -> 777000000000000022339D00CE516A3D9055111230CB4409004AE600740114206A8900A002003120150F292F94273116
MSI-470-Hynix-Stock-1625 -> 999000000000000022559D0010DE7B4480551312B78C450A004C0601750414206A8900A00200312018112D34A42A3816
MSI-470-Hynix-Stock-1750 -> 999000000000000022559D0031627C489055131339CDD50A004C06017D0514206A8900A00200312019123037AD2C3A17
MSI-470-Hynix-Stock-2000 -> BBB000000000000022889D0073EE8D53805515133ECF560C004E26017E0514206A8900A0020031201C143840C5303F17
------------------------------------------------------------------------------------------
Strap (RAS)                           trc    trcdr   trcdra    trcdw   trcdwa     trrd 
------------------------------------------------------------------------------------------
MSI-470-Hynix-Stock-1125               47       15       15       11       11        5 
MSI-470-Hynix-Stock-1250               52       17       17       12       12        5 
MSI-470-Hynix-Stock-1375               57       19       19       14       14        5 
MSI-470-Hynix-Stock-1425               59       20       20       14       14        6 
MSI-470-Hynix-Stock-1500               61       20       20       14       14        6 
MSI-470-Hynix-Stock-1625               68       23       23       16       16        7 
MSI-470-Hynix-Stock-1750               72       24       24       17       17        7 
MSI-470-Hynix-Stock-2000               83       27       27       19       19        8 
------------------------------------------------------------------------------------------
Strap (CAS)                           tcl    tnopr    tnopw     tr2r     tr2w     tw2r 
------------------------------------------------------------------------------------------
MSI-470-Hynix-Stock-1125               13        0        0        5       20       15 
MSI-470-Hynix-Stock-1250               15        0        0        5       22       15 
MSI-470-Hynix-Stock-1375               17        0        0        5       24       17 
MSI-470-Hynix-Stock-1425               17        0        0        5       24       17 
MSI-470-Hynix-Stock-1500               18        0        0        5       25       17 
MSI-470-Hynix-Stock-1625               18        0        0        5       24       19 
MSI-470-Hynix-Stock-1750               19        0        0        5       25       19 
MSI-470-Hynix-Stock-2000               19        0        0        5       24       21 
------------------------------------------------------------------------------------------
Strap (MISC)                         tcke     trfc      trp   trprda   trpwra 
------------------------------------------------------------------------------------------
MSI-470-Hynix-Stock-1125                0       55        9        9       40 
MSI-470-Hynix-Stock-1250                0       61       10       10       44 
MSI-470-Hynix-Stock-1375                0       68        2       10       46 
MSI-470-Hynix-Stock-1425                0       70       10       11       47 
MSI-470-Hynix-Stock-1500                0       74        2       11       48 
MSI-470-Hynix-Stock-1625                0       82        2       12       55 
MSI-470-Hynix-Stock-1750                0       86       10       13       57 
MSI-470-Hynix-Stock-2000                0       98       11       15       62 
------------------------------------------------------------------------------------------

Zorg33

jr. member

Activity: 144

Merit: 2

OK, I found the main timings finally... that was tough af, almost no sleep.

Wolf0

member

Activity: 81

Merit: 1002

It was only the wind.

Quote from: kilo17 on January 25, 2017, 02:52:43 AM

Quote from: kilo17 on January 21, 2017, 01:19:01 AM

Quote from: kilo17 on January 21, 2017, 12:41:33 AM

Quote from: Brewins on January 21, 2017, 12:24:56 AM

You guys are funny, I bet none of you have figured out all 20 of those timings. It is tough as shit to figure out- here's a challenge for you 3- if you kilo, jstefanop and eliovp can each post one of the following 3 timings from The Stilts Hyinx 1250 strap- I will then be a believer, otherwise I say you're all full of shit/

1 - tWR
2 - tWTR
3 - tRCDR

Good luck

- that's funny. I will do one- how about tWTR - it really doesn't matter to me

I changed my mind, I am going to post the tRTW to prevent giving away to much info - the tRTW in the following Stilt strap is 21

77 71 33 20 00 00 00 00 08 39 47 2A 50 55 0C 0B 24 20 45 04 00 46 C4 00 22 BB 1C 00 5C 0B 14 20 4A 89 00 A0 00 00 01 20 12 0C 21 1E 51 19 26 13

tRCDR - 0xE.

Correct me if I wrong, based on compare of custom straps from The Stilt with original one. Timing info contain in the string 77 71 33 20 00 00 00 00 08 39 47 2A and possible it's magic 3 registers one of them last or first is MC_SEQ_RAS_TIMING

MC_SEQ_RAS_TIMING is a bunch of timings, not just 1.

Ofc it's a 32 bit register where each value 4 bit. I've just want to know where exactly in this 48 byte strap this register. Also what about MC_SEQ_CAS_TIMING register, any interesting there?

Each value is not 4-bit, just some of them are.

dallase

member

Activity: 129

Merit: 10

Quote from: Zorg33 on January 29, 2017, 05:43:57 PM

Quote from: dallase on January 27, 2017, 02:34:52 PM

Quote from: dallase on January 27, 2017, 02:34:52 PM

SEQ_RAS [2 2 14 14 2 42] right?

edited... think i messed up b4

TNOPW 1
TNOPR 0
TR2W 21
TR2R 1
TW2R 6
TCL 19

I parsed all the 32bit segments as the MC_SEQ_CAS_TIMING reference says but none of them has the values you mentioned.
Are these calculated with or without the value offsets (e.g CAS to read data return latency - 2).
So 19 is actually 19+2 or already with the offset 17+2? Neither seems good, it should be somewhere around 14.

By the way none of the 32bit segments seems plausible, I think there must be some other trick too.
Something with the order of the bits? (MSB-LSB?)

Too many combinations, I almost spent my whole day again on this.

Nobody said my results were right...

Zorg33

jr. member

Activity: 144

Merit: 2

Quote from: Zorg33 on January 29, 2017, 12:26:55 PM

SEQ_RAS [2 2 14 14 2 42] right?

edited... think i messed up b4

TNOPW 1
TNOPR 0
TR2W 21
TR2R 1
TW2R 6
TCL 19

I parsed all the 32bit segments as the MC_SEQ_CAS_TIMING reference says but none of them has the values you mentioned.
Are these calculated with or without the value offsets (e.g CAS to read data return latency - 2).
So 19 is actually 19+2 or already with the offset 17+2? Neither seems good, it should be somewhere around 14.

By the way none of the 32bit segments seems plausible, I think there must be some other trick too.
Something with the order of the bits? (MSB-LSB?)

Too many combinations, I almost spent my whole day again on this.

dallase

member

Activity: 129

Merit: 10

I also spent almost two days already on this matter and it is though indeed...
I think I could identify RAS and CAS timing 32 bit straps and also some of the individual timings in them, but...
I can't find the Hynix AJR datasheet, (i'm using the AFR one), and I also can't find the register reference guide for the polaris GPU (or even the Sea Islands series would be great).
Any hints?

Code:

MC_SEQ_RAS_TIMING - RW - 32 bits - MCIND:0x61
TRCDW    4:0 5bit    Number of cycles from active to write
TRCDWA   9:5 5bit    Number of cycles from active to write with auto-precharge
TRCDR  14:10 5bit    Number of cycles from active to read
TRCDRA 19:15 5bit    Number of cycles from active to read with auto-precharge 
TRRD   23:20 4bit    Number of cycles from active bank a to active bank b
TRC    30:24 7bit    Number of cycles from active to active/auto refresh

#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x1f
#define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x0     5 bits

#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x3e0
#define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x5    5 bits

#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x7c00
#define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0xa     5 bits

#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0xf8000
#define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0xf    5 bits

#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0xf00000
#define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x14     4 bits

#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000
#define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x18      7 bits


MC_SEQ_CAS_TIMING - RW - 32 bits - MCIND:0x62
TNOPW    1:0 2bit    Extra cycle(s) between successive write bursts
TNOPR    3:2 2bit    Extra cycle(s) between successive read bursts
TR2W     8:4 5bit    Read to write turn
TCCDL   11:9 3bit    Cycles between r/w from bank A to r/w bank B.
TR2R   15:12 4bit    Read to read time
TW2R   20:16 5bit    Write to read turn
----   23:21 3bit    Unused.
TCL    28:24 5bit    CAS to data return latency


#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x3
#define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x0    # 2 bit

#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0xc
#define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x2    # 2 bit

#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x1f0
#define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x4     # 5 bit

#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0xe00
#define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x9    # 3 bit

#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0xf000    # 4 bit
#define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0xc     

#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x1f0000  # 5 bit
#define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x10

#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000 # 5 bit
#define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x18 


MC_SEQ_MISC_TIMING - RW - 32 bits - MCIND:0x63

TRP_WRA   5:0  6bit   From write with auto-precharge to active - 1.
----      7:6  2bit   Unused
TRP_RDA  13:8  6bit   From read with auto-precharge to active - 1.
----    16:14  3bit   Unused
TRP     19:16  4bit   Precharge command period - 1.
TRFC    26:20  7bit   Auto-refresh command period - 1.
TCKE    31:28  4bit   CKE power down exit timer.

#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x3f     
#define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x0        # 6 bit
 
#define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x3f00
#define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x8        # 6 bit

#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0xf8000
#define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0xf            # 4 bit

#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000
#define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x14          # 7 bit

# TCKE is not defined in gmc_8_1_sh_mask.h as a SEQ_MISC_TIMING

Zorg33

jr. member

Activity: 144

Merit: 2

I also spent almost two days already on this matter and it is though indeed...
I think I could identify RAS and CAS timing 32 bit straps and also some of the individual timings in them, but...
I can't find the Hynix AJR datasheet, (i'm using the AFR one), and I also can't find the register reference guide for the polaris GPU (or even the Sea Islands series would be great).
Any hints?

dallase

member

Activity: 129

Merit: 10

SEQ_RAS [2 2 14 14 2 42] right?

edited... think i messed up b4

TNOPW 1
TNOPR 0
TR2W 21
TR2R 1
TW2R 6
TCL 19

kilo17

legendary

Activity: 980

Merit: 1001

aka "whocares"

Quote from: Wolf0 on January 25, 2017, 03:12:43 AM

Quote from: kilo17 on January 25, 2017, 02:52:43 AM

Quote from: kilo17 on January 21, 2017, 01:19:01 AM

Quote from: kilo17 on January 21, 2017, 12:41:33 AM

Quote from: Brewins on January 21, 2017, 12:24:56 AM

You guys are funny, I bet none of you have figured out all 20 of those timings. It is tough as shit to figure out- here's a challenge for you 3- if you kilo, jstefanop and eliovp can each post one of the following 3 timings from The Stilts Hyinx 1250 strap- I will then be a believer, otherwise I say you're all full of shit/

1 - tWR
2 - tWTR
3 - tRCDR

Good luck

- that's funny. I will do one- how about tWTR - it really doesn't matter to me

I changed my mind, I am going to post the tRTW to prevent giving away to much info - the tRTW in the following Stilt strap is 21

77 71 33 20 00 00 00 00 08 39 47 2A 50 55 0C 0B 24 20 45 04 00 46 C4 00 22 BB 1C 00 5C 0B 14 20 4A 89 00 A0 00 00 01 20 12 0C 21 1E 51 19 26 13

tRCDR - 0xE.

Correct me if I wrong, based on compare of custom straps from The Stilt with original one. Timing info contain in the string 77 71 33 20 00 00 00 00 08 39 47 2A and possible it's magic 3 registers one of them last or first is MC_SEQ_RAS_TIMING

MC_SEQ_RAS_TIMING is a bunch of timings, not just 1.

Ofc it's a 32 bit register where each value 4 bit. I've just want to know where exactly in this 48 byte strap this register. Also what about MC_SEQ_CAS_TIMING register, any interesting there?

Each value is not 4-bit, just some of them are.

SEQ_RAS [2 2 14 14 2 42] right?

no

Wolf0

member

Activity: 81

Merit: 1002

It was only the wind.

Quote from: dallase on January 24, 2017, 03:15:40 PM

Quote from: Wolf0 on January 24, 2017, 12:59:45 PM

Quote from: Metroid on January 24, 2017, 09:36:19 AM

I had great results few months ago, making hynix to have elpida performance in few algo, + hynix had an even great performance with my own custom latency numbers.

I've gotten over 900H/s stable on XMR with my 470 4G - so yeah, it's pretty nice.

I assume thats overclock + custom timings?

Whats best rate on underclock/undervolt + custom timings?

That's actually overclock + undervolt + custom timings. It'll clear 850 easy with very conservative clocks.

zigun

newbie

Activity: 21

Merit: 0

Quote from: Wolf0 on January 25, 2017, 03:12:43 AM

Quote from: kilo17 on January 25, 2017, 02:52:43 AM

Quote from: kilo17 on January 21, 2017, 01:19:01 AM

Quote from: kilo17 on January 21, 2017, 12:41:33 AM

Quote from: Brewins on January 21, 2017, 12:24:56 AM

You guys are funny, I bet none of you have figured out all 20 of those timings. It is tough as shit to figure out- here's a challenge for you 3- if you kilo, jstefanop and eliovp can each post one of the following 3 timings from The Stilts Hyinx 1250 strap- I will then be a believer, otherwise I say you're all full of shit/

1 - tWR
2 - tWTR
3 - tRCDR

Good luck

- that's funny. I will do one- how about tWTR - it really doesn't matter to me

I changed my mind, I am going to post the tRTW to prevent giving away to much info - the tRTW in the following Stilt strap is 21

77 71 33 20 00 00 00 00 08 39 47 2A 50 55 0C 0B 24 20 45 04 00 46 C4 00 22 BB 1C 00 5C 0B 14 20 4A 89 00 A0 00 00 01 20 12 0C 21 1E 51 19 26 13

tRCDR - 0xE.

Correct me if I wrong, based on compare of custom straps from The Stilt with original one. Timing info contain in the string 77 71 33 20 00 00 00 00 08 39 47 2A and possible it's magic 3 registers one of them last or first is MC_SEQ_RAS_TIMING

MC_SEQ_RAS_TIMING is a bunch of timings, not just 1.

Ofc it's a 32 bit register where each value 4 bit. I've just want to know where exactly in this 48 byte strap this register. Also what about MC_SEQ_CAS_TIMING register, any interesting there?

Each value is not 4-bit, just some of them are.

SEQ_RAS [2 2 14 14 2 42] right?

zigun

newbie

Activity: 21

Merit: 0

Quote from: kilo17 on January 25, 2017, 02:52:43 AM