I guess its fair to say that I'm a bit nervous about Labcoin; a result of having a lot invested and not getting any of the fundamental questions answered..
Did anyone figure out an explanation/theory to the following already? Quoting from the somewhat dated
http://www.labcoin.com/presentation.html page, the initial road map was to have a 180nm chip with estimated ~250Mhash performance ready in August/September, and their second generation chip of 65nm at estimated 4-5 ghash at a later date... And from that they went to 130nm but with the same hash speed they targeted for the second generation chip?
I guess my gut feeling tells me that the chips will not perform even close to the 4ghash performance announced, however, it might still be profitable.. just not as profitable as projected..
The technology, version 1
Specifications:
Feature size : 180nm
Core voltage : 1.8V
I/O voltage : 3.3V
Core Frequency: 250 Mhz - vdd 1.8~1.85V
Number of Pads : 44
Package : LQFP or equivalent
Chip size : 5mm x 5mm
Power consumption (variable) : 1.4~1.8W
Hashing power (variable): 220~280 MH/second
I/O interface : USB / Serial
Estimated tape-out : Within the first half of July
The technology, version 2
Specifications:
Feature size : 65nm
Core voltage : n/a
I/O voltage : n/a
Core Frequency: n/a
Number of Pads : n/a
Package : n/a
Chip size : n/a
Power consumption (variable) : n/a
Hashing power (variable): estimated 4~5 GH/second
I/O interface : USB / Serial
Estimated tape-out : n/a
That's an easy one! Just simulate for 300MH/s and then multiply everything by 16 and you're done, since it all scales flawlessly!
Today we have a
very important update, the Chinese team is simulating a lot of design simultaneously and worked almost non-stop for the last 48 hours targeting different process sizes.
The results are more than positive, i will try to outline them in the clearest way possible.
1) The 65nm 500Mhz is still undergoing post-verification phase, while another simulation is ongoing at 600Mhz and we're waiting for the results.
2) Post simulations yielded
positive results on a 130nm, 300Mhz, Power 0.8W, 6.5x6.5mm design.
The team is working on HDL optimizations to get 16 cores for chip.
Some math, quoted from the tech team
"300M*16=4.8G, 0.8*16=12.8W, Area=130,0000*16=2080,0000, make the utilization ratio to 50%, the chip size will be about 4160,0000um2, about 6.5mm x 6.5mm"
"Power consumption per GHash is 12.8W/4.8G=2.7W/GHash"
"Estimated selling price for chip, 8-9 USD"
What does this mean ? i think it's not hard to get. 130nm process and 5GH speed at slightly higher power consumption, but competitive prices.
Shoot any question guys
Sam
Labcoin team
Power usage scaling linearly... Love it!
