Technical Details (Translated from various Bitfury Posts)
Each chip is capable of 2.8-10.4Gh/s using a 756 core design
Estimated Chip Power Consumption: 1.96-7.26W (0.7W per 1Gh/s)
Estimated Power Consumption at Wall: 1.4W per 1Gh/s (<200W per 120Gh/s Device)
- The design is built on the 65nm UMC Process (http://www.umc.com/English/process/a.asp)
- Bitcoin Engines: 756 Rolled cores (65 Cycles per Hash)
- Expected operational frequency: 250Mhz-900Mhz
- Packaging: QFN48
- Conservative design, could be 40% smaller
- Risk interconnect and transistor variations +/- 20%
- Core implemented using full custom design process (some global place & route)
- Number of transistors per "core": 55,000
- Power estimate obtained from hspice simulation
- Design optimised for low power and minimum size rather than high clock rate
Each chip is capable of 2.8-10.4Gh/s using a 756 core design
Estimated Chip Power Consumption: 1.96-7.26W (0.7W per 1Gh/s)
Estimated Power Consumption at Wall: 1.4W per 1Gh/s (<200W per 120Gh/s Device)
In case ppl don't know, a "sea-of-gates" chip is also a type of structured ASIC where only the metal layer needs to be customized.
