Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013) - page 9.

asjfdlksfd

full member

Activity: 128

Merit: 100

Quote from: goxed on May 20, 2013, 07:30:37 PM

BTW, can the Minimodule plus work without the baseboard or is the baseboard required to make the MMP work?

You need the power for the module and a connection.
If you implement an core for the attached usb plug or the ethernet interface on the MMP board possible you can use the communication over there so only power is needed.
So only jtag communication is additionally needed which looks like been possible only via the baseboard plugs.
The easiest is to use the baseboard + power module. But if you can lead an cheaper own delevoped base board it should been relative easy to create an power distribution board for the needed core and io voltage also, but I'm unsure which all voltages are needed.
The're pdc supports 1.0V 1.2V 1.8V 2.0V 2.5V and 3.3V but not all should been needed.
Jtag could been implement with an standard digilent JTAG-SMT-1 board USB board es well (est. 50$) which avnet and xilinx uses, too.
(needs 2.5V + 3.3V)
usb-uart should been possible over baseboard for easy access via SLL CP2102-GM (avnets chip) or cp2103 (kc705 chip). Power could been come only best from usb port for that chip.

Avnet have all the manuals and sheets available for registred customers here:
http://www.em.avnet.com/en-us/design/drc/pages/supportanddownloads.aspx?RelatedId=605
I'm sorry that I cannot give a direct copy.

If you are interested in one of my MMP modules send an pm.

gingernuts

member

Activity: 89

Merit: 10

Quote from: goxed on May 20, 2013, 07:30:37 PM

BTW, can the Minimodule plus work without the baseboard or is the baseboard required to make the MMP work?

It needs some sort of baseboard to supply it with the 8 different power supply voltages it wants - Avnet seem to want $500 for the baseboard and $300 for the PSU board, so it might be worth the effort of designing your own, especially as the MMP FPGA board seems to sell below the cost of a 7k325 FPGA, and seems to come with a license file to unlock the 7k325 device in the Xilinx tools!

The MMP board does look interesting, but it seems to only have 10A 1.0v core supply - can someone please tell me what the current KC705 design is using at 400MH/s?

goxed

legendary

Activity: 1946

Merit: 1006

Bitcoin / Crypto mining Hardware.

BTW, can the Minimodule plus work without the baseboard or is the baseboard required to make the MMP work?

goxed

legendary

Activity: 1946

Merit: 1006

Bitcoin / Crypto mining Hardware.

Quote from: asjfdlksfd on May 20, 2013, 06:48:42 PM

Hi,

I've used the KC705 design for the AVNet MMP KC7T325 to get an running bitstream today.
I've both, the KC705 and the AVNet MMP http://www.em.avnet.com/en-us/design/drc/Pages/Mini-Module-Plus-Development-Kit-Supporting-the-Kintex-7-FPGA-Family.aspx.

I've bougth to of the modules for only 600 € per board which is an good price, but it is not so fast as the KC705.
It will produce after a couple of time much more invalid shares although the temp is nearby the same as by the KC705.

The code itself looks like mostly compatible but only the kc705_pins.xdc has been changed to:

Code:

set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_p}]
set_property IOSTANDARD LVDS [get_ports {sys_clk_p}]
set_property LOC AA10 [get_ports {sys_clk_p}]

set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_n}]
set_property IOSTANDARD LVDS [get_ports {sys_clk_n}]
set_property LOC AB10 [get_ports {sys_clk_n}]

set_property IOSTANDARD LVCMOS25 [get_ports {uart_rx}]
set_property LOC U22 [get_ports {uart_rx}]
set_property IOSTANDARD LVCMOS25 [get_ports {uart_tx}]
set_property LOC V22 [get_ports {uart_tx}]

I couldn't find an design for that modules for vivado so I used as target design simple xc7k325tffg676-1 which I guessed is soldered.

Generally also the code is working on cheap AVNet MMP, too, but not with the effency at 400 MHz. I think it should been decrease by a small value but I've not the experience to do that at the moment with the given hashing clock multiplier.

My last question: I saw that there is already an design finished wich use only less than the half of DSPs so two of the rings could been implemented instead of one, so the mining is doubled?

Cheers...

I think the problem is that Avnet MMP uses -1 speed grade FPGA while KC705 uses -2 speed grade. Try to configure the clock generator for lower clock speeds for hash_clock down from 400MH to 375MHz, 350MHz, etc.

asjfdlksfd

full member

Activity: 128

Merit: 100

Hi,

I've used the KC705 design for the AVNet MMP KC7T325 to get an running bitstream today.
I've both, the KC705 and the AVNet MMP http://www.em.avnet.com/en-us/design/drc/Pages/Mini-Module-Plus-Development-Kit-Supporting-the-Kintex-7-FPGA-Family.aspx.

I've bougth to of the modules for only 600 € per board which is an good price, but it is not so fast as the KC705.
It will produce after a couple of time much more invalid shares although the temp is nearby the same as by the KC705.

The code itself looks like mostly compatible but only the kc705_pins.xdc has been changed to:

Code:

set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_p}]
set_property IOSTANDARD LVDS [get_ports {sys_clk_p}]
set_property LOC AA10 [get_ports {sys_clk_p}]

set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_n}]
set_property IOSTANDARD LVDS [get_ports {sys_clk_n}]
set_property LOC AB10 [get_ports {sys_clk_n}]

set_property IOSTANDARD LVCMOS25 [get_ports {uart_rx}]
set_property LOC U22 [get_ports {uart_rx}]
set_property IOSTANDARD LVCMOS25 [get_ports {uart_tx}]
set_property LOC V22 [get_ports {uart_tx}]

I couldn't find an design for that modules for vivado so I used as target design simple xc7k325tffg676-1 which I guessed is soldered.

Generally also the code is working on cheap AVNet MMP, too, but not with the effency at 400 MHz. I think it should been decrease by a small value but I've not the experience to do that at the moment with the given hashing clock multiplier.

My last question: I saw that there is already an design finished wich use only less than the half of DSPs so two of the rings could been implemented instead of one, so the mining is doubled?

Cheers...

dexX7

legendary

Activity: 1106

Merit: 1026

Sorry to hijack this thread with my noobish question, but could someone tell me roughly how many basic logic units (no adders for example) are used here? Thanks and great project!

goxed

legendary

Activity: 1946

Merit: 1006

Bitcoin / Crypto mining Hardware.

Quote from: fpgaminer on May 03, 2013, 05:20:06 PM

I've been asked a few times about a mining script for the current KC705 firmware. I wrote a plugin for Modular Python Bitcoin Miner. Here's the message I sent to someone about it:

Quote

I uploaded the custom MBPM module, which is compatible with the current KC705 mining code, here:
https://mega.co.nz/#!Oh5HTDRB!C0RLYW4yZN8gbg38FfgLpzmKFcseOql3Xx1i_gXTfdM

You'll want to download a copy of MPBM's testing branch. Then extract the above archive into
Code:
modules/fpgamining
such that you end up with:

Code:
modules/fpgamining/kc705_uart/__init__.py
modules/fpgamining/kc705_uart/kc705uartworker.py

Once you start MPBM, you can now add a KC705 Worker by openning up the MPBM web-interface (http://127.0.0.1:8832) and clicking the "Workers" button on the left. On Windows, I ran MPBM under Cygwin, and the "Port" ended up being /dev/com2 for me. The Baudrate is 115200.

~fpgaminer

I haven't had a chance to clean it up and put it on the repo yet.

+1

Okay here are the steps for Windows environment that I followed

a) Compile / Implement / Generate bitstream for KC705 board using Xilinx Vivado tool.

b) use iMpact to download the bitstream to 7k325

c) Install cygwin

d) Install python using cygwin installer (setup.exe)

e) download pyserial and install pyserial with python running inside Cygwin

e.1) make sure your kc705 serial port is COM1

f) download MPBM, and add the kc705 uart source in the recommended directories

g) run MPBM

h) create new Kc705 uart worker

i) mine!

razorfishsl

sr. member

Activity: 399

Merit: 250

Quote from: blackarrow on May 19, 2013, 09:48:14 AM

Hi!

My company, Black Arrow Limited is taking Bitcoin mining very seriously. We are currently producing Lancelot boards and have the facilities and experience to manufacture them at the best possible price and the experience to commercialize them.

We want to make faster and cheaper hardware for crypto-currencies.

At the moment we're looking into developing a more efficient (per $) FPGA hashing board than Lancelot (Spartan 6). We are also trying to build a team of FPGA engineers to make this happen.

I see that there are a lot of talented FPGA engineers so if you are interested in joining us, please PM me with your CV or work.

I think you need to do WAY more research... at >2GH/s pay back is currently $10USD a day putting even the cheapest FPGA at several hundred days for ROI.

The issue is NOT VHDL or 'engineering' but rather the base cost Vrs return on the FPGA.
Absolutely the CHEAPEST way to do FPGA mining is by buying EBAY scrap, but even that is a declining 30days ROI. Putting me safely in the goldilox zone of 100 days.

Even your own Lancelot >4 months before ROI, plus you are talking a DELAY of 2 MONTHS before you can deliver this....
Which makes your ROI 6 months.......

blackarrow

hero member

Activity: 532

Merit: 500

Hi!

My company, Black Arrow Limited is taking Bitcoin mining very seriously. We are currently producing Lancelot boards and have the facilities and experience to manufacture them at the best possible price and the experience to commercialize them.

We want to make faster and cheaper hardware for crypto-currencies.

At the moment we're looking into developing a more efficient (per $) FPGA hashing board than Lancelot (Spartan 6). We are also trying to build a team of FPGA engineers to make this happen.

I see that there are a lot of talented FPGA engineers so if you are interested in joining us, please PM me with your CV or work.

xbaby

newbie

Activity: 16

Merit: 0

Quote from: xbaby on May 10, 2013, 12:52:28 AM

the 300MHz result was just compiled with no timing error. in next few days, I'll program it on board to see if it could really run perfectly.

some update on the latest progress:

I must say the 300MHz result was achieved with no clock pin constrained. after bind the clock pin to real pin location (and I use a 25MHz crystal), It's very hard to meet above timing parameter. the best result I've achieved is 275MHz by now. a little bit strange.

And, to make my xc6vlx130t board actually work with a mining pool, I finished some hard work. the jtag_comm.v jtag / host communication code has some issue on Virtex6 BSCAN engine, and I've made a patch for it. currently, the board can work perfectly using the MPBM host software, with hash rate about 280MH/s, and about 11w wall power usage for 1 pcs lx130t FPGA chip.

Ersch

newbie

Activity: 5

Merit: 0

does anybody already try this board ARRIA II, 2AGX260, FPGA, DEV KIT ?

senseless

hero member

Activity: 1118

Merit: 541

Quote from: asjfdlksfd on May 18, 2013, 06:08:41 AM

I have a problem to download from sh... mega Angry

.
I cannot allready find the module on github. Is there another source?

Cheers..

Posted it for you

https://github.com/senseless/Modular-Python-Bitcoin-Miner/tree/testing/modules/fpgamining

asjfdlksfd

full member

Activity: 128

Merit: 100

Quote from: fpgaminer on May 03, 2013, 05:20:06 PM

I uploaded the custom MBPM module, which is compatible with the current KC705 mining code, here:
https://mega.co.nz/#!Oh5HTDRB!C0RLYW4yZN8gbg38FfgLpzmKFcseOql3Xx1i_gXTfdM

I have a problem to download from sh... mega Angry

.
I cannot allready find the module on github. Is there another source?

Cheers..

hagenees

newbie

Activity: 35

Merit: 0

Can anybody help to compile miner for ztex-1.11 board, I have no ideas how to make it.

fizzisist

hero member

Activity: 720

Merit: 528

There are a few tabs mixed in there. That should cause problems on some systems: lines 324, 331, 333, 334, 338. The 'bytes' issues are definitely due to using python3: http://docs.python.org/3.0/whatsnew/3.0.html#text-vs-data-instead-of-unicode-vs-8-bit

Should be easy enough to fix that up, though. Throw the code up on github and I'm sure someone will do it.

senseless

hero member

Activity: 1118

Merit: 541

Quote from: fpgaminer on May 12, 2013, 03:44:52 AM

Quote

Have you tested the code on windows? Having a hell of a time trying to get mining.

Weird. I have tested it on Cygwin, using Python 2.7. Maybe Python 3 doesn't like the code?

Working perfectly under cygwin with py 2.7, thank you.

fpgaminer

hero member

Activity: 560

Merit: 517

Quote

Have you tested the code on windows? Having a hell of a time trying to get mining.

Weird. I have tested it on Cygwin, using Python 2.7. Maybe Python 3 doesn't like the code?

senseless

hero member

Activity: 1118

Merit: 541

Quote from: fpgaminer on May 03, 2013, 05:20:06 PM

I've been asked a few times about a mining script for the current KC705 firmware. I wrote a plugin for Modular Python Bitcoin Miner. Here's the message I sent to someone about it:

Quote

I uploaded the custom MBPM module, which is compatible with the current KC705 mining code, here:
https://mega.co.nz/#!Oh5HTDRB!C0RLYW4yZN8gbg38FfgLpzmKFcseOql3Xx1i_gXTfdM

You'll want to download a copy of MPBM's testing branch. Then extract the above archive into
Code:
modules/fpgamining
such that you end up with:

Code:
modules/fpgamining/kc705_uart/__init__.py
modules/fpgamining/kc705_uart/kc705uartworker.py

Once you start MPBM, you can now add a KC705 Worker by openning up the MPBM web-interface (http://127.0.0.1:8832) and clicking the "Workers" button on the left. On Windows, I ran MPBM under Cygwin, and the "Port" ended up being /dev/com2 for me. The Baudrate is 115200.

~fpgaminer

I haven't had a chance to clean it up and put it on the repo yet.

Have you tested the code on windows? Having a hell of a time trying to get mining. Tried as best I could without knowing python to get it running without much success. First was getting a ton of indentation errors. PyWin editor was telling me 1/2 the code was not idented properly. Think I fixed those successfully; now getting the following errors. Any idea?

I was thinking it was a result of my python setup in windows [since another user was able to get it running under linux on the VC707]. Tried 3.3 and 3.2 with same errors on both.

Code:

2013-05-11 00:10:32.222 [100] KC705: Traceback (most recent call last):
  File "c:\FPGA Work\Scripts\mpm\modules\fpgamining\kc705_uart\kc705uartworker.py", line 201, in main
   self._sendjob(job)
  File "c:\FPGA Work\Scripts\mpm\modules\fpgamining\kc705_uart\kc705uartworker.py", line 391, in _sendjob
   self.handle.write(job.data[64:76].encode('hex') + job.midstate.encode('hex') + "\n")
AttributeError: 'bytes' object has no attribute 'encode'

2013-05-11 00:10:32.223 [100] KC705: Traceback (most recent call last):
  File "c:\FPGA Work\Scripts\mpm\modules\fpgamining\kc705_uart\kc705uartworker.py", line 323, in _listener
   data_buffer += self.handle.read(9)
TypeError: Can't convert 'bytes' object to str implicitly

When running the code default without changing any of the indentations I get:

Code:

2013-05-11 00:41:46.872 [300] Core: Could not load module fpgamining.kc705_uart: Traceback (most recent call last):
  File "c:\FPGA Work\Scripts\mpm\core\core.py", line 108, in __init__
   module = getattr(__import__("modules.%s" % maintainer, globals(), locals(), [module], 0), module)
  File "c:\FPGA Work\Scripts\mpm\modules\fpgamining\kc705_uart\__init__.py", line 1, in
   from .kc705uartworker import KC705UARTWorker
  File "c:\FPGA Work\Scripts\mpm\modules\fpgamining\kc705_uart\kc705uartworker.py", line 324
   if '\n' not in data_buffer: continue
   ^
TabError: inconsistent use of tabs and spaces in indentation

xbaby

newbie

Activity: 16

Merit: 0

the 300MHz result was just compiled with no timing error. in next few days, I'll program it on board to see if it could really run perfectly.

iidx

newbie

Activity: 35

Merit: 0

Possibly, but I used some compiler directives to force SRLs and registers in certain situations so the design would fit. In XST it infers too many of register or SRL to properly fit, so some manual instantiation might be required.

I'm still surprised that the Ztex project would hit 300 Mhz without extra pipeline stages. I think that it might be better to add DSPs to that project instead?

Topic: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013) - page 9. (Read 432965 times)