dose anyone know if there is a program for a mppa board ? i have a ambric am2040 mppa board that has 340 processing cores and wanted to use this for bitcoin mining i was told if i can get it up and running it could do about 18g/hash's but im new to the programming and fpga area and have only used gpu to mine any help would be appreciated
You won't get anything running on that board. Ambric went out of business in 2008, and none of the hardware is supported anymore. You can't get the programming tools for it.
Topic: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013) - page 4. (Read 432891 times)
July 09, 2013, 03:33:27 AM
July 08, 2013, 08:00:25 PM
dose anyone know if there is a program for a mppa board ? i have a ambric am2040 mppa board that has 340 processing cores and wanted to use this for bitcoin mining i was told if i can get it up and running it could do about 18g/hash's but im new to the programming and fpga area and have only used gpu to mine any help would be appreciated
July 08, 2013, 05:06:10 PM
Hi I've got a board with Altera EP4CE40F23I7N, so 40K LE. With CONFIG_LOOP_LOG2 = 3, I was able to compile the code. But I see that there is a lot of free LE. It is just being used 61% of all LE. based on that scenario I have 3 questions:
1) How can I simulate/calculate how many mh/s does this boad?
2) I have to set the correct to PIN to my board. The vendor gave me a PIN table and I have to ajust the clock PIN. looking to the table, It looks to be the PIN under CLK_INPUT more specifically the 50M PIN_AB11. Does it make sense? I've got this 50M to believe that it is a 50MHZ..
3) What should I look into to try to optimize the code? My goal would be to be able to compile with CONFIG_LOOP_LOG2 = 2 and be able to fit my code into the board..
thank you, awesome stuff
1) How can I simulate/calculate how many mh/s does this boad?
2) I have to set the correct to PIN to my board. The vendor gave me a PIN table and I have to ajust the clock PIN. looking to the table, It looks to be the PIN under CLK_INPUT more specifically the 50M PIN_AB11. Does it make sense? I've got this 50M to believe that it is a 50MHZ..
3) What should I look into to try to optimize the code? My goal would be to be able to compile with CONFIG_LOOP_LOG2 = 2 and be able to fit my code into the board..
thank you, awesome stuff
July 01, 2013, 04:49:03 PM
thank you!
July 01, 2013, 04:30:42 PM
Hi, there is any version of the open source FPGA Bitcoin Miner that is able to communicate over USB and not UART?
hm I checked now and my FPGA comes with this USB that means, its able to speak UART or am I missing something here?
hm I checked now and my FPGA comes with this USB that means, its able to speak UART or am I missing something here?
Yes, that should be fine. In fact, many commercial FPGA miners (such as BFL) use UART in the same way, with integrated USB-serial adapters such as the EZ-USB.
UART is used in the FPGA scene, because it is much simpler than full USB. However, most modern computers do not have real serial ports, so we end up using those adapters.
July 01, 2013, 10:07:58 AM
Hi, there is any version of the open source FPGA Bitcoin Miner that is able to communicate over USB and not UART?
hm I checked now and my FPGA comes with this USB http://www.cypress.com/?id=193 that means, its able to speak UART or am I missing something here?
hm I checked now and my FPGA comes with this USB http://www.cypress.com/?id=193 that means, its able to speak UART or am I missing something here?
June 30, 2013, 12:10:51 PM
I added a timeout on the serial_receive to improve recovery after invalid input is encountered. I figure 65535 cycles at 109MHz is around 7 bytes worth at 115200 baud.
https://github.com/tmackay/Open-Source-FPGA-Bitcoin-Miner/tree/cgminer
Seems to be chugging along nicely at present. I can even echo gibberish to the serial ports and it recovers well.
https://github.com/tmackay/Open-Source-FPGA-Bitcoin-Miner/tree/cgminer
Seems to be chugging along nicely at present. I can even echo gibberish to the serial ports and it recovers well.
Nice! While this hasn't solved my problems with some quirky serial ports, I can see it is generally useful, and I'd like to merge it back to my repo. Problem is, I'm not well versed in git... so perhaps you could make a pull request?
Edit: Thanks, merged
June 21, 2013, 10:05:32 AM
I added a timeout on the serial_receive to improve recovery after invalid input is encountered. I figure 65535 cycles at 109MHz is around 7 bytes worth at 115200 baud.
Yeah, I did pretty much the same thing on my code. Its been mining reliably for several months now on a range of (small) devices, just never seems to go out of sync. I wrote my own driver (for raspi serial port) so the golden nonce receive also has a timeout, plus hash verification. I've recently been looking to use cgminer 3.1.1 as a driver (somebody asked for it), but its giving me grief (I need to drop the speed to 4800 baud as I'm using a slow opto-isolator interface, and its just not playing ball at the moment).
PS My thanks to teknohog for the original code, and for his recent mods for icarus support.
[EDIT] FYI, other than the need to tweak the read timeout settings, the cgminer problem was due to the fpga ignoring the very first work packet sent. I don't know if this is a quirk with using a physical serial port on my raspi rather than the USB driver cgminer expects, or due to a problem with my/teknohog's serial rx code. The fix was simply to send the test work twice (with a slight delay), before waiting on the returned nonce. Cgminer 3.1.1 now works at 4800 baud on a raspi physical serial port.
June 20, 2013, 08:45:19 PM
Regarding the Versa board, I downloaded the Lattice software (and the special license for the Versa board), and threw the stock Verilog project at it, running the PLL at 50 MHz. It couldn't fit LOOP_LOG2 = 2, I had to use LOOP_LOG2 = 3 like I am using for my smaller Cyclone III board. Although there is definitely more room to spare in this new Lattice part, so someone with a smaller algorithm might make it work more efficiently. I spent very little time working with it....
June 20, 2013, 08:29:00 PM
While we're discussing comms, it would be great to agree on a semi-standard serial protocol for all these opensource projects. If there are enough users, a driver for cgminer could be written. The current solution with the Icarus driver is not very reliable.
I've been trying this code with 4 DE2-115 boards attached to a BeagleBone using the 4 easily available UARTS. They tend to fall over after a day or so. I suspect at some point a byte is dropped on the serial interface sending the receive buffer out of sync.
I added a timeout on the serial_receive to improve recovery after invalid input is encountered. I figure 65535 cycles at 109MHz is around 7 bytes worth at 115200 baud.
https://github.com/tmackay/Open-Source-FPGA-Bitcoin-Miner/tree/cgminer
Seems to be chugging along nicely at present. I can even echo gibberish to the serial ports and it recovers well.
June 19, 2013, 03:16:05 AM
Is there a porting guide for the Verilog/VHDL code or miner to another different FPGA (ie different vendor/size etc)?
Thanks.
Do you have any specific board that you want to target?
Yes, specifically the LatticeECP3 Versa (with a ECP3-35) but ECP3 family in general.
http://www.latticesemi.com/products/developmenthardware/developmentkits/ecp3versadevelopmentkit/index.cfm
ECP3 a 4-input LUT FPGA, like the Virtex-4. SPARTAN-6 is a 6-input LUT FPGA so the logic capacity requirements would be much higher LUT count for ECP3. A fully pipelined hasher may or may not fit this FPGA, fully pipelined dual sha-256 is almost unlikely.
http://www.xilinx.com/support/documentation/white_papers/wp284.pdf
June 18, 2013, 09:28:12 PM
Interesting, I didn't think Lattice had any cheap boards. I don't think Lattice routes as well as Altera, but I haven't worked at all with ECP3. This might require some investigation....
June 18, 2013, 01:40:11 AM
Quote
WOW! For $99 :
http://www.latticestore.com/searchresults.aspx?supplieruvid=55850000&searchstring=LFE3-35EA-VERSA-EVN
which is based on LFE3-35EA-8FN484C - you get 33K LUTs ...
on one hand - it isn't much, but on the other - for that much money ... it is tempting!
http://www.latticestore.com/searchresults.aspx?supplieruvid=55850000&searchstring=LFE3-35EA-VERSA-EVN
which is based on LFE3-35EA-8FN484C - you get 33K LUTs ...
on one hand - it isn't much, but on the other - for that much money ... it is tempting!
Just for development & feasibility for now. Could be looking at a larger board + FPGA later on. More of a DIY educational project.
There are many FPGA based projects on sale already OR taken off the market because of the ASIC's emergence.
June 18, 2013, 01:31:23 AM
Is there a porting guide for the Verilog/VHDL code or miner to another different FPGA (ie different vendor/size etc)?
Thanks.
Do you have any specific board that you want to target?
Yes, specifically the LatticeECP3 Versa (with a ECP3-35) but ECP3 family in general.
http://www.latticesemi.com/products/developmenthardware/developmentkits/ecp3versadevelopmentkit/index.cfm
WOW! For $99 :
http://www.latticestore.com/searchresults.aspx?supplieruvid=55850000&searchstring=LFE3-35EA-VERSA-EVN
which is based on LFE3-35EA-8FN484C - you get 33K LUTs ...
on one hand - it isn't much, but on the other - for that much money ... it is tempting!
June 17, 2013, 10:17:05 PM
Is there a porting guide for the Verilog/VHDL code or miner to another different FPGA (ie different vendor/size etc)?
Thanks.
Do you have any specific board that you want to target?
Yes, specifically the LatticeECP3 Versa (with a ECP3-35) but ECP3 family in general.
http://www.latticesemi.com/products/developmenthardware/developmentkits/ecp3versadevelopmentkit/index.cfm
June 17, 2013, 08:00:37 PM
Is there a porting guide for the Verilog/VHDL code or miner to another different FPGA (ie different vendor/size etc)?
Thanks.
Do you have any specific board that you want to target?
June 17, 2013, 11:58:08 AM
Is there a porting guide for the Verilog/VHDL code or miner to another different FPGA (ie different vendor/size etc)?
Thanks.
June 17, 2013, 12:23:42 AM
A few months ago I saw on those forums a topic about mining with it .. and I can't find it now
I did add a bookmark the place to buy it from :
http://www.terasic.com.tw/cgi-bin/page/archive.pl?No=593
and on the good side - it is only $79 or academic for $59 from them.
In a nutshell the topic discussed that - yes you could start mining with it, but due to the limited resources you shouldn't expect more than 5-20MH/s. Still an interesting experiment though.
EDIT: I was looking for another link that I spotted recently. If you're seriously looking into getting into FPGA mining - maybe this one will make more sense:
http://www.cardreaderfactory.com/shop/lancelot.html
for $350 (+$70 shipping for up to 4pcs) you get 2 x Xilinx FPGA XC6SLX150 (speed grade -3, -3N or -2) which for about 26W produces approx. 400MH/s. And they seem to have those in stock.
June 16, 2013, 01:16:30 PM
June 16, 2013, 12:29:58 PM
Ah, it looks like the code I was using was from a different fork! I'll check out yours.....
Jump to: