Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013) - page 6.

goxed

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Quote from: senseless on June 01, 2013, 05:50:30 PM

Quote from: goxed on May 31, 2013, 07:15:34 AM

Can you please point me to the hashing code that you used? I want to program my 7K325 on KC705 board with that code and check its performance. Thanks

It was the OrphanGland stratix IV code ported over to the K7. We were planning on making an FPGA device but the power utilization vs hash vs cost figures weren't as close to the avalon figures as we had hoped.

Is that code the same on fpgaminer's github project or is there another link? Any link would be great. Thanks!

senseless

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Quote from: goxed on May 31, 2013, 07:15:34 AM

Can you please point me to the hashing code that you used? I want to program my 7K325 on KC705 board with that code and check its performance. Thanks

It was the OrphanGland stratix IV code ported over to the K7. We were planning on making an FPGA device but the power utilization vs hash vs cost figures weren't as close to the avalon figures as we had hoped.

Ascendion

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I've been asked to look into the feasibility of packing a core on to an XC3S50 and wanted to ask here before diving into trying to synth it myself. From what I've seen in the repo and this thread that device is probably far too small even for a tightly rolled hasher, but I'd like to hear it from the experts

It doesn't matter how many cycles it takes per hash, just asking if it can be made to fit at all period. The person I'm asking for has some 500 of these chips sitting in a box

asjfdlksfd

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Quote from: senseless on May 31, 2013, 06:17:21 AM

I was able to achieve 1Gh/s (5 cores @ 200mhz w/ +0.1 timing) but not using fpgaminer's code and the code wasn't complete (didnt actually hash, comm wasn't migrated), but yes it is possible. I was able to achieve 450Mh/s on the A7 200.

It should be possible to get 1.2Gh/s out of the K7 and probably around 600 with the A7 (If you give it a little bit of help on the fit.)

Do you like to share the code?

fpgaminer

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Quote

Okay I tried the 600MH/s bitstream on a second Kintex-7 325T device and the temps are 70C. For the record in the same environment the other Kintex-7 325 chip hovers at 30 - 35C in the same setting.

For curosity's sake, you could measure the heatsink's temperature. If both heatsinks are the same temp, it's likely your "special" FPGA either has a broken temp sensor (as gingernuts mentioned), or perhaps calibration is off (I think those sensors can be calibrated?). If the temps are drastically different ... well ... I guess you won the FPGA lottery Tongue

goxed

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Quote from: senseless on May 31, 2013, 06:17:21 AM

Quote from: goxed on May 31, 2013, 01:29:26 AM

I have a question regarding fpga mining on the 7K325T FPGA. Is there a project / bitstream which can mine at or greater than 1GH/s on this FPGA?

I was able to achieve 1Gh/s (5 cores @ 200mhz w/ +0.1 timing) but not using fpgaminer's code and the code wasn't complete (didnt actually hash, comm wasn't migrated), but yes it is possible. I was able to achieve 450Mh/s on the A7 200.

It should be possible to get 1.2Gh/s out of the K7 and probably around 600 with the A7 (If you give it a little bit of help on the fit.)

Can you please point me to the hashing code that you used? I want to program my 7K325 on KC705 board with that code and check its performance. Thanks

senseless

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Quote from: goxed on May 31, 2013, 01:29:26 AM

I have a question regarding fpga mining on the 7K325T FPGA. Is there a project / bitstream which can mine at or greater than 1GH/s on this FPGA?

I was able to achieve 1Gh/s (5 cores @ 200mhz w/ +0.1 timing) but not using fpgaminer's code and the code wasn't complete (didnt actually hash, comm wasn't migrated), but yes it is possible. I was able to achieve 450Mh/s on the A7 200.

It should be possible to get 1.2Gh/s out of the K7 and probably around 600 with the A7 (If you give it a little bit of help on the fit.)

goxed

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Bitcoin / Crypto mining Hardware.

I have a question regarding fpga mining on the 7K325T FPGA. Is there a project / bitstream which can mine at or greater than 1GH/s on this FPGA?

goxed

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I will hook up a Kill-a-Watt and check both the boards with the same bitstream.
It is a proxy, but not perfect measurement for power differences.

gingernuts

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Quote from: goxed on May 29, 2013, 02:24:43 PM

Okay I tried the 600MH/s bitstream on a second Kintex-7 325T device and the temps are 70C. For the record in the same environment the other Kintex-7 325 chip hovers at 30 - 35C in the same setting.
So I pretty much guess Xilinx is downselling some of the higher performing chips which can be good if these chips are bought in bulk and can be user-binned.

I don't suppose you know whether one of those chips is an engineering sample - it'll have ES as part of the speed grade?

My guess is that one of those two chips has a duff temp sensor or XADC - I can't believe they are selling chips with 2x the power consumption randomly! I guess you'd need to be able to monitor the core-current to actually know what the power really is!

goxed

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Okay I tried the 600MH/s bitstream on a second Kintex-7 325T device and the temps are 70C. For the record in the same environment the other Kintex-7 325 chip hovers at 30 - 35C in the same setting.
So I pretty much guess Xilinx is downselling some of the higher performing chips which can be good if these chips are bought in bulk and can be user-binned.

kingcoin

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Quote from: razorfishsl on May 28, 2013, 05:16:55 PM

Just wondering if Xilinx lets very high grade parts thru as lower grade when they are running short.....

They all do. The yield will in most cases improve as the process and tooling matures. They don't de-tune the process to produce slower parts. As for "Easypath" they might end up selling perfect devices as discounted defective devices.

razorfishsl

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Check the version number on the FPGA.
you can do it by reading the chip ID.

I have found a MASSIVE difference in power/heat & speed using the SAME part numbers and specs and bitfiles, but on reading the internal chip details the FPGA's have different revision numbers.......

Just wondering if Xilinx lets very high grade parts thru as lower grade when they are running short.....

kingcoin

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Quote from: goxed on May 28, 2013, 03:22:45 AM

I have a question about compiling sha256_pipes2.v under Vivado. It compiles fine under Xilinx ISE, but vivado seems to not like this source, it always points the following line with syntax error.

Code:

for (i = 0; i <= STAGES; i = i + 1) begin : S

Anyone got this verilog source to compile in Vivado?

I haven't read that file, but in general if that is part of a generate statement you have to make sure that you have made Vivado accept Verilog-2001, SystemVerilog or whatever version of Verilog your syntax corresponds to. From a TCL script you can read the file using something like this:

Code:

 read_verilog -sv sha256_pipes2.v

goxed

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I have a question about compiling sha256_pipes2.v under Vivado. It compiles fine under Xilinx ISE, but vivado seems to not like this source, it always points the following line with syntax error.

Code:

for (i = 0; i <= STAGES; i = i + 1) begin : S

Anyone got this verilog source to compile in Vivado?

goxed

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Quote from: fpgaminer on May 25, 2013, 07:29:39 PM

Quote

I have requested a pull for the open-source fpga project on github.

Hello goxed! I just checked your pull requests. There are no code changes in them. One just adds a file named "600MHz" with the text "600MHz" in it. The other is the same. There must have been a mistake somewhere.

Hey thanks for letting me know. my bad! I think I have to learn how to correctly use github.

goxed

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Quote from: asjfdlksfd on May 26, 2013, 11:49:35 AM

Quote from: gingernuts on May 26, 2013, 04:36:55 AM

Given that the Spartan 6 150's on other mining boards burn ~10W and only run at ~27C under a small (40mm squared) heat sink and moderate airflow, I would have thought that the Kintex is far more likely to be running at around 30C than 70C. If it is burning 10W then that heatsink and fan would have to have a thermal resistance of 5C/W to get the chip that hot - and that's pretty crappy for a heatsink with a fan...

As I remember Spartan-6 has no internal temp measuring, isn't it? My Spartan-6 boards on by both mq boards said round about 40 °C at room temp of 25 °C = 15 K difference. But they have an gpu cooler with an 6cm diameter.

The KC705 cooler with running fan tastes more than 40 °C (my finger means it's nasty warm, not to leave them to long on the cooler). So the internal +50 K looks like is a fact.
I checked the coolers stats from malico.com.tw web site (30x30x6 = MLT30-06) which I've measured. The stats says for that cooler an resistance of 4.82 K/W @ 200LFM to 2.4 K/W @ 600LFM. I'm unshure whats LFM means.
The Fan is 30x30 mm². I've found an titan TFD-3007M12S which could have 5m³/h (2,95cfm).
I guess with values + internal resistance ~ 4K/W at >12W on chip looks like is not so much aside from you calculation.

The cooler on MMP K7 boards which runs only on 350 MHz because of the limited pdc tastes warm round about <40°C, but not hot. With <8W and reported internal 55° C that's consistence to the KC705.

I will search my PT100 thermometer to check the temp later on cooler, but I guess that the high results are a fact.

I tried to start chipscope but never did this before and have problems how to do that Sad

Hey can you please report your KC705 VccInt from either XADC / chipscope or a DMM? Mine's 1.05V

goxed

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Quote from: gingernuts on May 26, 2013, 04:36:55 AM

Given that the Spartan 6 150's on other mining boards burn ~10W and only run at ~27C under a small (40mm squared) heat sink and moderate airflow, I would have thought that the Kintex is far more likely to be running at around 30C than 70C. If it is burning 10W then that heatsink and fan would have to have a thermal resistance of 5C/W to get the chip that hot - and that's pretty crappy for a heatsink with a fan...

The KC7k325T kintex-7 FPGA on my KC705 board has consistent temps between 25 to 35C hashing as 600MH/s. I am using the default heatsink, and reading temps off the chipscope. I will soon have access to another kc705, and will report its temps once ii is set up.

asjfdlksfd

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Quote from: asjfdlksfd on May 22, 2013, 08:48:54 AM

Quote from: asjfdlksfd on May 22, 2013, 08:02:14 AM

Quote from: gingernuts on May 21, 2013, 06:21:36 PM

Thanks for that - according to the manual the MMP power board only has 6A of VCCINT - which at 1.0v is just 6W Sad

- have you got a fan you can point at the regulator chips?

I've bought TI Simple switcher board for the AVNET. I'm unsure how much amperes they can deliver. At the moment I've downclocked to 350 MHz and got now stable near by 350 MHs without invalid nonces anymore.
Viavados Report Power means the chip needs aprox. 7.4 W but it's still the DSP design from the site.

Now I understand why I get invalid nonces...:

Xilinx power bank / FMC Voltage	Voltage (V)	Max Current (A)	Tolerance
Vccint/Vccbram	1	6	3.00%
Vcco	1.5 / 1.35	4	5.00%
Vccaux/Vccaux_io/Vccadc/Vcco/MGTVccaux	1.8	6	5.00%
Vccaux_io	2	2	3.00%
Vcco	2.5	8	5.00%
Vcco	3.3	8	5.00%
MGTAVcc	1	6	3.00%
MGTAVtt/MGTAVTTrcal	1.2	4	2.50%

I'm unsure we will get more power to the mmp by resoldering the second 1V line. Maybe or not... Tongue

But generally it is better to use 1V with an higher rate. I guess again D12F200A looks good and costs are not so high (est. 19 EUR + VAT + transport).

It's a little bit more complex than expected. I checked the simple switcher board and checked the documentation for Vccint/bram and MGTAVcc 1.0 V rails.
Both are descriped with an max. current of 6 A, but both rails from the pdc board supports only the fpga core.
So official the max. current is 2x 6A supported from TI LM21212 for fpga. But in fact also the LM21212 supports up to 12A and not only 6A described in TIs documentation for these chips.

On PDC board the LM21212s gets there power from the 3.3V rail with a max. current of 16.5A. 2x 12A at 1V should been possible so I think the LM21212s are limited to supports only 6A+ by an setup on pdc board. Possible this could been changed.
In fact of that it is possible to use 12W for the FPGA it should been possible to implement an bitstream design which supports more than 350 MHz as in the moment with an better balance so between both rails the current ist better balanced.
It is easier to use only one rail with 20 A :/

asjfdlksfd

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Quote from: gingernuts on May 26, 2013, 04:36:55 AM

Given that the Spartan 6 150's on other mining boards burn ~10W and only run at ~27C under a small (40mm squared) heat sink and moderate airflow, I would have thought that the Kintex is far more likely to be running at around 30C than 70C. If it is burning 10W then that heatsink and fan would have to have a thermal resistance of 5C/W to get the chip that hot - and that's pretty crappy for a heatsink with a fan...

As I remember Spartan-6 has no internal temp measuring, isn't it? My Spartan-6 boards on by both mq boards said round about 40 °C at room temp of 25 °C = 15 K difference. But they have an gpu cooler with an 6cm diameter.

The KC705 cooler with running fan tastes more than 40 °C (my finger means it's nasty warm, not to leave them to long on the cooler). So the internal +50 K looks like is a fact.
I checked the coolers stats from malico.com.tw web site (30x30x6 = MLT30-06) which I've measured. The stats says for that cooler an resistance of 4.82 K/W @ 200LFM to 2.4 K/W @ 600LFM. I'm unshure whats LFM means.
The Fan is 30x30 mm². I've found an titan TFD-3007M12S which could have 5m³/h (2,95cfm).
I guess with values + internal resistance ~ 4K/W at >12W on chip looks like is not so much aside from you calculation.

The cooler on MMP K7 boards which runs only on 350 MHz because of the limited pdc tastes warm round about <40°C, but not hot. With <8W and reported internal 55° C that's consistence to the KC705.

I will search my PT100 thermometer to check the temp later on cooler, but I guess that the high results are a fact.

I tried to start chipscope but never did this before and have problems how to do that Sad

Topic: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013) - page 6. (Read 432965 times)