Topic: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013) - page 5. (Read 432891 times)

I've ported some of my projects to work with cgminer, and they work with some limitations. The same idea did not work with my little Nexys2 -- it's probably too slow. If you have a somewhat faster FPGA, you could try one of these

https://github.com/teknohog/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/DE2_115_makomk_serial_109mhz_cgminer
https://github.com/teknohog/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/DE2_115_cluster_cgminer
https://github.com/teknohog/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/Xilinx_cluster_cgminer

In the cluster projects, simply build with one local miner and total miners = 1 to get a standalone version.

Hello! I just started mining a few weeks ago, I have been using a spare Cyclone III dev board that I "borrowed" from work. It's too small for real mining, but good enough to get my feet wet.

I used the "Xilinx Verilog Port" project and did a basic port to Quartus and it works. But I had to piece together my own getwork mining script, and it's not tremendously stable: after a few days, it stops being able to get more work and I don't know why. Simply restarting the mining script makes everything work again. Using the Stratum proxy in between doesn't seem to help, either.

I'm not really looking to make any money on this (I think I missed the boat, should have done this in 2010), but I am really looking at this as an opportunity to expose myself to Verilog again.

What is the current State Of The Art in the fpgaminer project? I see the KC705 and Kintex projects have been touched most recently. Would either of these projects integrate better with cgminer or one of the other available miners? I can't help but think my setup would be better if I were using someone else's miner software, since my Python mining script sucks.

As a side note, I need to buy a board soon to replace my borrowed board. I don't necessarily want to pay full price for a DE2-115, and the new Xilinx boars all seem too expensive as well, so I guess it's either hit eBay or hope for cheap Cyclone V boards....

Thank you!

Just a standard aluminum block with fins about 3cm tall , BUT with about  17CFM.. airflow
Only issue is  I have to keep brushing the cat pubes out of the  fins.

It is AIRFLOW...... and keeping the inductors cool.
I run the miners 24/7 but at night I turn off the 'aircon', but even during the day its set to 30 which gives an ambient of about 28
In the morning it is easily 40 deg. c but it is not a problem...

DO NOT overlook DIRECT cooling the DC/DC convertors  a drift of .2v on the core can shove the temp up exponentially.

Yep....
At this sort of speed it only takes 0.1 of a volt before you are issuing invalid nonces.
I've thrown a lot of research into FPGA power supplies, as seen on some of these miner boards.

It's either get into temperature compensated PSU's or cool the local board environment.
One other issue is that some of these DC/DC power supplies have a limit resistor at which point the core voltage collapses down.

This is why some of these FPGA's just stop working at a certain frequency... it's not actually the FPGA or the logic, but rather
The current limit on the DC/DC has cut in.

The Virtex range will happily come close to 300MHZ ~300MH/s on a -1 grade part..... IF you control the core voltage AND the temp.

Thanks for the suggestions.  I improved the cooling and they have been stable for a few days now.

Are you using the kc705? If yes, which heatsink did you use? How are you cooling the VRM / PSU? I have placed the board next to an AC vent, but that;s not a sustainable solution.

Yes it is, and my ultimate plan is to make the board into a self contained miner using a small microblaze with Linux.

Anybody managed to shrink the code to under 6k LE using a loop of 5 on an altera device? I get around 7k and am looking at places to shrink it... So far it's 50% logic, 50% registers...

First of all, I've changed my DE2-115 cgminer project to use the uart_* code from the KC705 project. It's nice to use something GPL3, and it was almost a drop-in replacement

While we're discussing comms, it would be great to agree on a semi-standard serial protocol for all these opensource projects. If there are enough users, a driver for cgminer could be written. The current solution with the Icarus driver is not very reliable.

My original project simply sent the golden nonce, it was enough for simple getwork, but not good in the long run. Icarus changed this to send zero for out-of-work, but it's not very good because zero is a valid nonce (though you can distinguish them from the timing). Also, it's nice to have some diagnostics (temperature). It's also easier if the return value is always of the same length. For example, 2 bytes for the type of return data and 4 bytes data (nonce, temperature etc.) would be a huge improvement.

you really need to slap some BIG heat sinks and BIG blowers on there.

Had a similar issue with the Xilinx development board, even with a blower, lifted off the Mickey mouse heat-sink.. dropped on one twice as tall and now it sits at about 53 deg.c
but it is CRITICAL you cool the SM PSU modules as well,  I notices as they get hot... they drift UPWARDS!!! taking the core-voltage out of spec and causing further serious heating of the FPGA (not to mention its possible destruction.....)

Which is why I had to throw in a 'system monitor" for both voltage and core temp...... then I had to split out the  CLK for the communication & the logic separately and gate the SHA256 logic to the  sys monitor..... (you cannot just gate the CLK, because it controls the FPGA internal function .. including the sys monitor...)

Then I dropped some mini heat-sinks (for ram chips) on-top of the inductors for the SM PSU and the thing is stable even at 40 deg c ambient!!!

Even allowing for the mains PSU efficiency, 45W seems a lot for a mere 600MH/s - 4x Spartan 6's will give you 800MH/s for the same power - I guess that demo board is burning loads in all the other stuff that's on the board (RAM/Ethernet etc)...

Nope, I am using 7K325T-2 @ 600MHz. Hash rates have been stable @ 600MH/s for > 1 week.

What was needed is active cooling (good airflow using fans) of the VRMs and FPGA.

The FPGA easily reaches > 70C, and in the absence of active cooling it sometimes stops working.

I've been mining with some 7K325T-1 parts running the KC705 code clocked at 300MHz for a couple of weeks now.  I notice that the hash rate starts to drop off after a day and a half and I have to restart the miners to get it to come back up.  Has anyone else seen this?

Great thanks!

It's all there in serial.v and fpgaminer_top.v. Read the spec too for an overview.

Edit: now using UART code from KC705_experimental.

Can you share the source code for the comm module? I will try to add it to the KC705 / Kintex-7 comm code.

I've got the DE2-115 miner working with cgminer:

https://github.com/teknohog/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/DE2_115_makomk_serial_109mhz_cgminer

I can do this for any project that uses my serial mining code. The reason is, as I only recently learned, that Icarus was based on my serial mining cluster project. There was only a small change in my protocol to facilitate Stratum etc:

http://en.qi-hardware.com/wiki/Icarus#Communication_protocol_V3

so I updated my code accordingly (from the spec, not Icarus code). Now the device can use the Icarus driver in cgminer, at least when timings etc. are set accordingly.

For some reason, I can only get this to work with cgminer version 3.1.1. Perhaps it's due to a quirky USB-serial converter -- I'll test with other hardware later.

Power consumption is same for both FPGA boards at 45Watts, 600MH/s.

 The one that shows lower temp probably has a poorly calibrated temp sensor. Reported temps are around 1/2 of the actual temp.

So this info solves this small mystery.

https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/VHDL_StratixIV_OrphanedGland

The port was pretty basic it was just to get it to compile and display correct timings during analysis.

Don't own a thermometer. Any other method that comes to mind?
 Most likely it's a calibration issue. Will plug it in a Kill-a-Watt first to get any anecdotal evidence (power consumption differences)