Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013) - page 8.

kingcoin

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Quote from: goxed on May 23, 2013, 07:24:46 AM

Nope the FIFO / BRAM doesn't meet timing specs. The Fmax for K7 speed grade -2 FIFO is 543.77MHz. But my FPGA still runs fine at 600MHz.
I guess it's stretching the limits. Also it could vary chip to chip, since -3 speed grade has a Fmax of 601.32MHz.

Thanks. I was wondering if the full fabric was running at 600MHz. BTW, was this using Vivado for synthesis?

goxed

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Quote from: kingcoin on May 23, 2013, 06:51:08 AM

Quote from: goxed on May 23, 2013, 05:31:48 AM

Quote from: kingcoin on May 23, 2013, 03:52:46 AM

Quote from: goxed on May 22, 2013, 08:58:22 PM

Just re-implemented the DSP design by fpgaminer for 600MHz operation. Nothing major. It needs -2 or -3 speed grade chips for that speed.

Is that a single hash core reporting 600MHz operation in the static timing analysis using a -2 speed device?

It's the KC705 experimental design from github which used DSP48E blocks on the K7. The reported speed is actual hashing speed.

Does the static timing analysis show that all paths are below 1.6ns? Or did you just check that your particular device runs at 600MHz?

Nope the FIFO / BRAM doesn't meet timing specs. The Fmax for K7 speed grade -2 FIFO is 543.77MHz. But my FPGA still runs fine at 600MHz.
I guess it's stretching the limits. Also it could vary chip to chip, since -3 speed grade has a Fmax of 601.32MHz.

http://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf, Pg 32, Table 31

kingcoin

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Quote from: goxed on May 23, 2013, 05:31:48 AM

Quote from: kingcoin on May 23, 2013, 03:52:46 AM

Quote from: goxed on May 22, 2013, 08:58:22 PM

Just re-implemented the DSP design by fpgaminer for 600MHz operation. Nothing major. It needs -2 or -3 speed grade chips for that speed.

Is that a single hash core reporting 600MHz operation in the static timing analysis using a -2 speed device?

It's the KC705 experimental design from github which used DSP48E blocks on the K7. The reported speed is actual hashing speed.

Does the static timing analysis show that all paths are below 1.6ns? Or did you just check that your particular device runs at 600MHz?

goxed

legendary

Activity: 1946

Merit: 1006

Bitcoin / Crypto mining Hardware.

Quote from: kingcoin on May 23, 2013, 03:52:46 AM

Quote from: goxed on May 22, 2013, 08:58:22 PM

Just re-implemented the DSP design by fpgaminer for 600MHz operation. Nothing major. It needs -2 or -3 speed grade chips for that speed.

Is that a single hash core reporting 600MHz operation in the static timing analysis using a -2 speed device?

It's the KC705 experimental design from github which used DSP48E blocks on the K7. The reported speed is actual hashing speed.

kingcoin

sr. member

Activity: 262

Merit: 250

Quote from: goxed on May 22, 2013, 08:58:22 PM

Just re-implemented the DSP design by fpgaminer for 600MHz operation. Nothing major. It needs -2 or -3 speed grade chips for that speed.

Is that a single hash core reporting 600MHz operation in the static timing analysis using a -2 speed device?

goxed

legendary

Activity: 1946

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Bitcoin / Crypto mining Hardware.

Quote from: asjfdlksfd on May 22, 2013, 09:14:42 PM

Quote from: goxed on May 22, 2013, 08:58:22 PM

Just re-implemented the DSP design by fpgaminer for 600MHz operation. Nothing major. It needs -2 or -3 speed grade chips for that speed.

Can you share the vivado files you've changed? Possible upload to https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects? I'm interested in to check them on my KC705.
Whats power consumption?

Link pmed.
I have requested a pull for the open-source fpga project on github. once approved i will upload the project there as well. Power on chip according to vivado is 12.5W.

asjfdlksfd

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Quote from: goxed on May 22, 2013, 08:58:22 PM

Just re-implemented the DSP design by fpgaminer for 600MHz operation. Nothing major. It needs -2 or -3 speed grade chips for that speed.

Can you share the vivado files you've changed? Possible upload to https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects? I'm interested in to check them on my KC705.
Whats power consumption?

goxed

legendary

Activity: 1946

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Bitcoin / Crypto mining Hardware.

Just re-implemented the DSP design by fpgaminer for 600MHz operation. Nothing major. It needs -2 or -3 speed grade chips for that speed.

asjfdlksfd

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Activity: 128

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Quote from: goxed on May 22, 2013, 07:44:11 PM

Hey I got the KC705 board working at 600MH/s. Anybody interested in the 600MH/s bitstream? I can share it for download.

It is possible to upload them to git?
What do you have changed? Is this still the DSP design or do you replaced some dsps by simple lut adders to become 2 parallel rings?

Cheers...

goxed

legendary

Activity: 1946

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Hey I got the KC705 board working at 600MH/s. Anybody interested in the 600MH/s bitstream? I can share it for download.

kingcoin

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Merit: 250

Quote from: kramble on May 21, 2013, 01:40:10 PM

Quote from: kingcoin on May 21, 2013, 12:52:56 PM

I've been getting a lot of these errors lately:

Code:

[05/22/2013 04:08:33] ERROR: Unable to getwork. Reason: can't read "state(status)": no such variable

Is this a common/known problem?

The getwork is timing out (probably the pool server is not responding). It happened a lot with BtCGuild when it was under DDOS attack. I changed to using a stratum proxy server which is much more stable. Just install the proxy from https://github.com/slush0/stratum-mining-proxy , configure it to point to your preferred pool and start it up. Then (assuming you're using the mine.tcl script) set the config.tcl to connect to localhost:8332 (leave the login details the same as the proxy just passes them through to the pool).

[EDIT] Oops. I just saw your other post at https://bitcointalksearch.org/topic/mining-proxy-212246 so it looks like you're on to this already. Anyway slush's proxy is pretty easy to set up (I'm using it on raspberry-pi linux).
Mark

It's better now. Hopefully the proxy will improve the situation further. Thanks!

asjfdlksfd

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Quote from: asjfdlksfd on May 22, 2013, 08:02:14 AM

Quote from: gingernuts on May 21, 2013, 06:21:36 PM

Thanks for that - according to the manual the MMP power board only has 6A of VCCINT - which at 1.0v is just 6W Sad

- have you got a fan you can point at the regulator chips?

I've bought TI Simple switcher board for the AVNET. I'm unsure how much amperes they can deliver. At the moment I've downclocked to 350 MHz and got now stable near by 350 MHs without invalid nonces anymore.
Viavados Report Power means the chip needs aprox. 7.4 W but it's still the DSP design from the site.

Now I understand why I get invalid nonces...:

Xilinx power bank / FMC Voltage	Voltage (V)	Max Current (A)	Tolerance
Vccint/Vccbram	1	6	3.00%
Vcco	1.5 / 1.35	4	5.00%
Vccaux/Vccaux_io/Vccadc/Vcco/MGTVccaux	1.8	6	5.00%
Vccaux_io	2	2	3.00%
Vcco	2.5	8	5.00%
Vcco	3.3	8	5.00%
MGTAVcc	1	6	3.00%
MGTAVtt/MGTAVTTrcal	1.2	4	2.50%

I'm unsure we will get more power to the mmp by resoldering the second 1V line. Maybe or not... Tongue

But generally it is better to use 1V with an higher rate. I guess again D12F200A looks good and costs are not so high (est. 19 EUR + VAT + transport).

asjfdlksfd

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Quote from: gingernuts on May 21, 2013, 06:21:36 PM

Thanks for that - according to the manual the MMP power board only has 6A of VCCINT - which at 1.0v is just 6W Sad

- have you got a fan you can point at the regulator chips?

I've bought TI Simple switcher board for the AVNET. I'm unsure how much amperes they can deliver. At the moment I've downclocked to 350 MHz and got now stable near by 350 MHs without invalid nonces anymore.
Viavados Report Power means the chip needs aprox. 7.4 W but it's still the DSP design from the site.

Are they allready updates with faster code available? I read here something but I'm unsure that they are allready uploaded.

hagenees

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Sorry, I repeat my question: can somebody help me to run minert on ztex fpga board 1.11?

goxed

legendary

Activity: 1946

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Bitcoin / Crypto mining Hardware.

Quote from: gingernuts on May 21, 2013, 06:21:36 PM

Quote from: goxed on May 21, 2013, 05:50:11 PM

Quote from: gingernuts on May 21, 2013, 03:17:30 AM

Quote from: goxed on May 20, 2013, 07:30:37 PM

BTW, can the Minimodule plus work without the baseboard or is the baseboard required to make the MMP work?

It needs some sort of baseboard to supply it with the 8 different power supply voltages it wants - Avnet seem to want $500 for the baseboard and $300 for the PSU board, so it might be worth the effort of designing your own, especially as the MMP FPGA board seems to sell below the cost of a 7k325 FPGA, and seems to come with a license file to unlock the 7k325 device in the Xilinx tools!

The MMP board does look interesting, but it seems to only have 10A 1.0v core supply - can someone please tell me what the current KC705 design is using at 400MH/s?

Xilinx vivado estimates the power draw of the 7K325 Chip is ~11W. It's infact hashing at 500MH/s right now with minor modification to the code. The VCCInt power module is getting a bit hot for my liking at 500MH/s. IMO the voltage reg chips on that module need heatsinks.

Thanks for that - according to the manual the MMP power board only has 6A of VCCINT - which at 1.0v is just 6W Sad

- have you got a fan you can point at the regulator chips?

So I am using the KC705 board, it's got a 1.0V @ 20A Vccint regulator. The chips are so small (smaller than my smallest thumbnails

) , that it's very difficult to affix a heatsink w/o shorting something. Any ideas would be appreciated. Right now I have placed the board next to the airconditioner.

gingernuts

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Quote from: goxed on May 21, 2013, 05:50:11 PM

Quote from: gingernuts on May 21, 2013, 03:17:30 AM

Quote from: goxed on May 20, 2013, 07:30:37 PM

BTW, can the Minimodule plus work without the baseboard or is the baseboard required to make the MMP work?

It needs some sort of baseboard to supply it with the 8 different power supply voltages it wants - Avnet seem to want $500 for the baseboard and $300 for the PSU board, so it might be worth the effort of designing your own, especially as the MMP FPGA board seems to sell below the cost of a 7k325 FPGA, and seems to come with a license file to unlock the 7k325 device in the Xilinx tools!

The MMP board does look interesting, but it seems to only have 10A 1.0v core supply - can someone please tell me what the current KC705 design is using at 400MH/s?

Xilinx vivado estimates the power draw of the 7K325 Chip is ~11W. It's infact hashing at 500MH/s right now with minor modification to the code. The VCCInt power module is getting a bit hot for my liking at 500MH/s. IMO the voltage reg chips on that module need heatsinks.

Thanks for that - according to the manual the MMP power board only has 6A of VCCINT - which at 1.0v is just 6W Sad

- have you got a fan you can point at the regulator chips?

goxed

legendary

Activity: 1946

Merit: 1006

Bitcoin / Crypto mining Hardware.

Quote from: gingernuts on May 21, 2013, 03:17:30 AM

Quote from: goxed on May 20, 2013, 07:30:37 PM

BTW, can the Minimodule plus work without the baseboard or is the baseboard required to make the MMP work?

It needs some sort of baseboard to supply it with the 8 different power supply voltages it wants - Avnet seem to want $500 for the baseboard and $300 for the PSU board, so it might be worth the effort of designing your own, especially as the MMP FPGA board seems to sell below the cost of a 7k325 FPGA, and seems to come with a license file to unlock the 7k325 device in the Xilinx tools!

The MMP board does look interesting, but it seems to only have 10A 1.0v core supply - can someone please tell me what the current KC705 design is using at 400MH/s?

Xilinx vivado estimates the power draw of the 7K325 Chip is ~11W. It's infact hashing at 500MH/s right now with minor modification to the code. The VCCInt power module is getting a bit hot for my liking at 500MH/s. IMO the voltage reg chips on that module need heatsinks.

kramble

sr. member

Activity: 384

Merit: 250

Quote from: kingcoin on May 21, 2013, 12:52:56 PM

I've been getting a lot of these errors lately:

Code:

[05/22/2013 04:08:33] ERROR: Unable to getwork. Reason: can't read "state(status)": no such variable

Is this a common/known problem?

The getwork is timing out (probably the pool server is not responding). It happened a lot with BtCGuild when it was under DDOS attack. I changed to using a stratum proxy server which is much more stable. Just install the proxy from https://github.com/slush0/stratum-mining-proxy , configure it to point to your preferred pool and start it up. Then (assuming you're using the mine.tcl script) set the config.tcl to connect to localhost:8332 (leave the login details the same as the proxy just passes them through to the pool).

[EDIT] Oops. I just saw your other post at https://bitcointalksearch.org/topic/mining-proxy-212246 so it looks like you're on to this already. Anyway slush's proxy is pretty easy to set up (I'm using it on raspberry-pi linux).
Mark

kingcoin

sr. member

Activity: 262

Merit: 250

I've been getting a lot of these errors lately:

Code:

[05/22/2013 04:08:33] ERROR: Unable to getwork. Reason: can't read "state(status)": no such variable

Is this a common/known problem?

asjfdlksfd

full member

Activity: 128

Merit: 100

Quote from: gingernuts on May 21, 2013, 03:17:30 AM

It needs some sort of baseboard to supply it with the 8 different power supply voltages it wants - Avnet seem to want $500 for the baseboard and $300 for the PSU board, so it might be worth the effort of designing your own, especially as the MMP FPGA board seems to sell below the cost of a 7k325 FPGA, and seems to come with a license file to unlock the 7k325 device in the Xilinx tools!

Yea, the license + the complete board could been a good base for an multi mmp baseboard in the way the mmq did.
The costs of the simple chips + bb design for e.g. an up to 4 (or Cool

plug board looks not so strange.
The board comes with some external memory so it could been possible to program them as ltc miner, too, but this is only an idea.
To use power modules for core and more it could been possible to use the D12F200A modules which generate 0.8 to 5 V at 40 A which should been enough for 2-3 mmp.
For the DDR and VCAUX possible only one voltage is needed. Which of them I will check later.

Topic: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013) - page 8. (Read 432950 times)