Topic: Swedish ASIC miner company kncminer.com - page 1607. (Read 3049505 times)

Ill grant you that, but I havent heard anyone refute hashfast's argument that the minimum estimate of KnC's die size based on the package/underfull dimensions would be on the order of 900mm³. Thats not just a little bit bigger, thats an epic size.


Please do also ask about the PCB testing with the cyclone fpga (see my last post edit at the end).  How come their "full custom" asic happens to be electrically and pin compatible with an altera cyclone IV (and therefore, hardcopy IV) if its not a hardcopy?

https://www.kncminer.com/userfiles/image/ASIC_PCB.jpg

It just doesnt seem very likely or credible to me.

edit: should have read the text better.

KNCminer ASIC is:

28nm standard cell ASIC mining chips (which are being designed exclusively for KnCMiner by ORSoC).

yes:)

We'll have to wait and see, hence time will demonstrate the fact, but I personally feel those that are late have to exaggerate as no one is interested in funding someone who errs on the side of caution this late in the game. Whether some have outright lied will also have to be seen. I don't think Cointerra are deceiving with respect to their delivery time, and that said, I think that honesty is harming them (in the short term as other competing manufacturers cash grab pre-orders), where upon I feel others are capitalising on being deceitful (read their terms and how they excessively go out of their way to distance them selves from any liability and accountability). Hence those that accept, and those that choose to go out of their way purposely avoid third party liability backed secured payment methods as at least a choice is a huge red flag. This is logical, and to me speaks volumes with respect to manufacturer integrity.

That said we only know KnC's package size, not die size. Large package size, does not necessarily correlate to a large die size. Although you wouldn't conversely be able to house a large dies in a small package, but there could be many reasons behind the choice. I could try and press them on this in a few days, but if they haven't mentioned it now, I presume they will likely be more cagey this time round when they have nothing more to prove than performance figures.

porad tomu veris?.)

3 working days monday is 30th, and 5 working days for KnC

still not chips and 2 working days left. lol.
on shedule for sure.

Their specs most certainly are, even compared to actual shipping 55nm products. That hashfast and cointerra and VMC and black arrow and Coincraft and BFL and whomever Im forgetting are all exaggerating remains to be seen (Ill grant you BFL) , but for bitfury we have tested numbers. Those numbers make  KnC's promised efficiency look anything but impressive and makes the other vendors claims for 28nm entirely believable.


which leads you to believe everyone except KnC is lying through their teeth about their specs, and which leads me to question if KnC are doing a full custom design.
btw, VMC is doing a structured ASIC and their efficiency projections are better than KnCs. OF course they may also be overly optimistic, but still.

Besides, you havent explained the die size.


How exactly would you tell? And how do you explain the picture of the PCB with a cyclone FPGA that was used to test the board? What are the odds a full custom asic would end up with the exact same compatible pinout as a cyclone/hardcopy?

If your competition is mining at 1Watt per GH/s or less,  then yes that's bad, as it means they can pump up the net hash until you can no longer afford to mine, and they still can, unless you can find cheaper electricity.

Can those asics be down clocked in order to improve the W per GH/s significantly ?
I'm not aware of infos regading this or I might have missed it somehow.

1.6W per GH/s seems quite bad in long term, no?

Cool, maybe I'll hold back from any new preorders for a couple weeks and accumulate some coins.  Ah but I forget!  I can actually use a CC to order from KNC.  

KnC have created a standard cell ASIC.

They aren't significantly worse GH/J than any other competing 28nm company, which has been my entire point the whole time.

The competing 28nm companies are using the same process, at the same node. Just KnC were first and have been honest, and realistic with their expectations, letting the evidence talk for itself when they have something to show.

The other competitors were months late and had to embellish upon marketing to tie up funds and promise figures based on best case simulations, just some have taken it a step further and been very dishonest.

28nm standard cell, is a 28nm standard cell, either you realise this now, or time will demonstrate this fact.

Sure KnC have probably employed margins that may have erred on the side of caution as they saw speed and mitigating risk as the main priority, but we are talking a minor percentage performance difference between competitors from the final result, not major as has been claimed.

That doesn't occur until the next major step down in geometry from 28nm.

I know KnC is on record saying this is a cell based asic, not a hardcopy. But that was said a long time ago, and  if you look at the known facts:

- significantly worse GH/J than competing 28nm (and even 55nm) chips,
- judging by the chip package, massive die size, ~3x larger per GH than cointerra and hashfast
- extremely fast TTM (assuming they meet their goals), with apparently no need for any chip testing
- Chip developed by a company with a trackrecord in doing altera harcopy conversion
- Originally planned to do an FPGA
- PCB tested/photographed with an altera cyclone FPGA that just happens to fit

I have a hard time believing this is not a hardcopy or some other structured asic.

(Note: Im not saying thats a bad thing. Its what I would have done too).

They said they would, and I dare say quite a few Mercury orderers would be pissed if they don't come good on that promise as it's been factored into some peeps purchase decisions

Yeah. I don't know why they chose not to do testing. I guess they figured they'd get the chips a day or two earlier without it.  Remember, there are four physically separated circuits on each die.  They're completely separate, the only difference between them an totally independent chips is the die isn't cut. I guess the theory is that it makes it cheaper to package/mount that way.

Anyway, it could be that KnC thinks its extremely unlikely that all four sub-chips will be bad, and therefore their plan is to mine with functional circuits on chips that have problems.

Seems like a reasonable plan to me.

I don't get why people are so obsessed with this - they are going to test the units before they send them to customers, and that's all that matters, right?

Does anyone know for sure if KNC will be selling expansion modules?  Right now I'm ordering a Bitfury board every time I accumulate enough BTC for another one.  I might put some aside if I knew that KNC was planning on adding them to the store soon.  I'll have 3 slots to fill since I only ordered a Mercury.

He was implying that they should do testing.

Then what would be the point of them spending their time generating test patterns that would never be run?

According to this thread they have clearly stated that they will not run test patterns on the chip tester.

And you are supposing that OrSoc, who is responsible for doing the chip production and testing, isn't clever enough to have thought of doing something like that?