This is mostly irrelevant to Bitcoin mining chips: they are so redundant and fault-tolerant, that they can use just about any technology that has working transistors ("working" in the analog sense of the word).
Fab problems for a top-flight light-house customers are actually moderately good for small, research-like customers doing Bitcoin mining: less competition for the limited wafer-start slots.
One SHA engine is simple, deceptively so, cram so many together on a chip and you get horrendous power and leakage issues that are more like multipipe GPUs than CPUs or SOCs or anything.
If it was sofa king straightforward, every SHA ASIC ever thought of so far would have come in below, even at power target, on time, or even at all. (AM had a fail, BFL had a fail. and don't forget they were working with reputable design and layout houses. And there might have been a couple of private venture flops we've never heard of)
You've got one guy who designed all Samsung top shit failing to get his projected 2Gh out of the cointerras for example. Hashfast approached the SHA ASIC game as "this is going to be a piece of piss" and got their fingers burned off to the shoulder.
Anyway, when you've gone out and made a SHA ASIC that came in on time, with power and frequency within even 30% of the theoretical capabilities of the process, then I'll let you tell me how simple SHA ASICs are to make.
