Topic: [Announcement] Avalon ASIC Development Status [Batch #1] - page 18. (Read 155335 times)

Why not, take out the USB cord and plug it into your computer instead, not sure if you want to do this though considering openWRT runs the miners just fine. e.g. cgminer. not to mention there are other airflow reasons you do not want to change the unit, unless you want to run a USB cord out of the unit to an external PC for example.


the openWRT controller is very similar to the TL-WR703n, you can plug in a USB storage if you want.


We are working with xiangfu, and you are correct. We have always practiced what we preach when it comes to open source. This time will be no different.

My guess is they'll have a configuration page where you can make edits to the parameters passed to cgminer. I do hope they'll let us ssh into it. If the past firmwares for OpenWRT for Icarus mining is any indication, ngzhang has always went the "be more open" route. I wonder if xiangfu is still around, he had a custom firmware for the 1043ND I used that I really enjoyed.

I have a few TL-WR703Ns around already, with their 4MB of flash.  I suppose I could add USB storage if more is needed.

I guess it's possible to solo mine without having to download and store the entire blockchain somewhere.  I've just never seen it done.  I imagine Avalon will just hook up to a pool server or a regular bitcoind node, and not by itself be capable of solo mining, correct?

Any update on avalon flash (will be good also 4/8/16 MB)/RAM(16/32/64/128) memory size (i guess there will be no HDD inside

The best will be flash > 4 and RAM >=64 personal opinion. With 8 Flash and 64 or 128 RAM we will be able to do whatever we like install php,web server, vpn or whatever comes handy
10X
PS: If i find a way to make proper cooling for asic unit and there is a hack (which will come with a time)  so that ASIC can be plugged in regular Linux PC i will take that route personally. But this option will not be available from day one though

No, it's got a miner in it already Which is most likely to be cgminer.

kano,

if I'm not wrong, Avalon, is a stand alone unit with an ethernet connection, it is not externally controlled by a miner.

spiccioli

Will the USB be like Icarus (PL2303) or something else?
I've been (very slowly) rewriting the cgminer drivers to use libusb, done MMQ, working on BFL, then if there is also a need Icarus.
The new ASIC drivers will of course be based on these USB versions (when I write them)

Huh, only just now? I thought they taped out early as September, we actually expected them to be online and mining since November. Looks like we over estimated all of our competition.


Yes, work is progressing on this end, I think I'll get you guys an update within this weekend or so. If anything we will release the openWRT image first and release the updated miner later. but it is not really any different than other Atheros AR7240 CPU, Atheros AR9331 Chipset routers.

Hurry up Avalon ! 

ASICMiner has got their ASIC chip. Check this please:  https://bitcointalksearch.org/topic/m.1422891

Yep. If they're on track, we should expect it within the next week or so.

Wasn't there to be a demo of some sort also?

Can't wait for it.

+1
You memory is perfectly correct:)

I would like to have it with quick build instructions how to build it from cvs open-wrt

If my memory is correct, Team Avalon said, that they will release system image for their hardware at the end of December. End of Dec. is here...

It leaves him gnashing his teeth, poor guy So much ego and so little to justify it.

I know that the above was meant to be a joke, but it helps to explain some salient choices that the designer has to make.

Most of the FPGA designers for Bitcoin hashing used the XC6SLX150 chip that has about 150k "gates" and costs about $200.

hardcore-fs is working on XC5VLX110T chip that has about 110k "gates" and costs about $2000.

So where's the catch? Spartan-6 has much less "wires" than Virtex-5, the designs on Spartan-6 are quite oftern routing-constrained: there is enough "gates", but not enough "wires" to connect them. And even if there is enough "wires" then the gate interconnections may be longer and slower than in a design that uses less "gates".

Check out the extreme example of the routing-resource limitation: eldentyrell started working on his "hand-placed, auto-routed" design in October'11. He complained about auto-routing failing and being forced to hand-route until about March'12 when he disclosed that he started using DSP slices for some adders to relieve the congestion of the routing for the general-purpose SLICEs.

https://bitcointalksearch.org/topic/m.793740

The very same conceptual limitations will apply to the ASIC synthesis. One can spend a lot of time optimizing performance for the particular design flow. Or one can accept most of the default choices to optimize the time it takes to start the manufacturing.

Put it through a pipeline the same length as the main calculation - no subtraction at all!

for Christ sake.
Why the hell do people assume you need to do a subtraction when  a 'nonce' is found, this is C programming at its worse, by people incapable of thinking in parallel.
Once again for the noobs:
The nonce is calculated BEFORE the SHA256(SHA256(x)), the product of this function is what is evaluated and dictates IF the nonce is a golden value.
Therefore you have ATLEAST 120 clk cycles to calculate the nonce correction (subtraction), before it is needed (if at  all)

The subtraction is only an issue for people that should not be programming logic chips in the first place.

If you have unused gates just "sitting around", please use them.

Here: http://betsofbitco.in/item?id=1003

and here: http://betsofbitco.in/item?id=1016

true enough..

lol.,  sorry i even mentioned it.. And no way to work around this?
Well, thats why you program that thing, right?. The information you give the synthesis tools reduces this space by very much.

Anyway, it would be too off-topic to discuss it here. I take it it is not an easy task.

The blackbox art of FPGA programming...

The overall speed of a pipelined logic design is limited by the speed of the slowest stage. In the design I mentioned the last pipeline stage did what every other stage did plus it did the zero comparator, subtractor and a latch.
I don't think you've ever tried to use Xilinx ISE or something similar. The problem isn't: come up with a different, potentially faster design. The problem is: come up with a working design, the one that the available tools will be capable of synthesizing, and placing/routing sensibly. The overall structure of SHA-2 (which makes every output bit depend on every input bit in each round) is apparently hitting some worst case behavior in the Xilinx toolchain. It takes close to a full day to run a single full implementation. And in many cases the the toolchain either fails to converge to a working implementation or converges to something shamefully inefficient.

On this board 2^256 is frequently thrown around as a number so high that nobody will be able check all of them. Compare this with the work demanded from the Xilinx placing tool: 23038 SLICEs in XC6SLX150 can be permuted in 23028! ways (I'm making a gross simplification of the "place" step) which is about 10^90499. Obviously all digital synthesis tools have to take some heuristic shortcuts through that vast space of available solutions.

So the human art required from the designer is to figuratively take the poor toolchain by the hand an lead it/them to some safe place.