Topic: [Announcement] Avalon ASIC Development Status [Batch #1] - page 30. (Read 155335 times)

Chinese New Year officially starts on the 8th of February and ends on the 14th, but this is a very big holiday in China. We do not expect things to return to normal until at least ten day later, which is our second batch expected shipping date.

Maybe I was misunderstood. BFL is probably getting around 1000 chips out of a 300mm wafer, so their order for a 100k chips would be about 100 wafers. The mask costs will be large, but ordering a couple to several hundred thousand dollars worth of wafers on top of your mask costs without doing a small run to test it just seems very risky.

That is a pretty damn honest reason. (Wish BFL would do the same!)

When does the Chinese New Year Holiday Start and End?

Ok, fair enough.

Let me explain to you what our timeline actually looks like, so you may get a better picture.

We plan to ship at Jan 14th, 2013. Hopefully finish shipping all 300 before Chinese New Year holiday. To foresee some potential problems, we originally announced we will finish shipping all 300 units before End of February 2013 for exactly this reason. Therefore, due to this holiday, we will have a large delay between when the second shipment can start, which is estimated at Feb 24th currently.

It is because we are so confident we will not be taking your money so early and not ship any goods, especially when it is some delay that is beyond our control.

never mind, it's just a option to avoid some unnecessary trouble. 

@ Ngzhang

Why does it say under one of the (online forms) that it failed the DRC check? (Design Rule Check)

Is that because you did something unusual with the chip that the DRC would fail the automatic checks?

i think the wafer cost is rather low than the MASK cost @ 65nm.. ...

I wonder what price BFL is getting their 300mm 65nm wafers for, if Avalon is paying 4k for a 110nm wafer? Even if they pay half of what Avalon is due to their higher volume, their 100k chip order would be worth $200k.
They better hope the chips work this time.

If you guys at Avalon are confident of your process, tech and timeline why wouldn't you open up more capacity to accept orders from disenchanted customers of competitors?

With the quality of disclosure coming from Avalon I'm starting to believe this to be true.  And I'm getting pissed.

Yeah, it seems its 50mm^2 packed:
So chip price will be something like 1usd and some pennies.

I thought they said their chips were 15mm²?

That would be a boatload of chips on a 300mm wafer.

Of course, I am simplifying and ignoring other costs: human resources (engineers), shipping, assembly, etc. And yes Avalon, as a standalone device, is a more complex/expensive than the competition devices, so add $100-150 to my numbers as I wasn't thinking about it. I have no doubt all ASIC companies are in the red initially. It will take you guys months to start being in the black. But after that point, you do agree with me that it will be mainly profits... (and good for you! or else you would not have started the business venture at all).

(PS: the number of chips per Avalon is mostly irrevelant to these price estimations. I estimate you will have about 500mm² of die area per Avalon device. Whether it is 10 x 50mm² chips or 20 x 25 mm² chips is irrelevant to my numbers. 500mm² of wafer space will cost $40 regardless.)

Actually this is very wrong, at this point in time, when we initially made the 300 order limitation, we were right at our break even point, and currently due to fees and other some problems, we are in fact in the red. Also while we can not reveal our chip numbers per unit, but it is much greater than 10 chips. Everyone is simply under the impression that 7GH/s chips are the "norm" due to what I believe to be false advertisement by the competition.

If you can get me those other components you mentioned like PCB, PSU and other stuff for 100-200 dollars maximum, maybe we should hire you to manage our component purchasing! a single good PSU is near $100...

Thank for sharing the info.

However you did not black out the top pixel line of the price digits, so we can still make them out by comparing them with other non-obscured digits in the document (I almost wonder if you did this intentionally):


Pilot / Engineering Wafer Lot Price = either $1x,xxx.xx or $4x,xxx.xx
Production Wafer Unit Price = $4,xxx.xx
Mask Set Price = $2xx,xxx


It is probably possible to make out some of the unknown 'x' digits by counting the spacing between the pixels, but I was too lazy to do it. The most significantly digit is the most important one anyway.

This price quote is a proof to people who don't believe that ASICs are cheap to manufacture, after NRE costs are recovered. A 12-inch wafer costs $4k for Avalon. They will likely make about a thousand chips per wafer assuming a 50 mm² die. Which means each chip technically costs about $4. There is going to be ten chips or so per Avalon device, so $40 of ASIC chips in a device that is sold $1300. That's a profit margin of $1260! (I am simplying here, there are other minor costs: chip packaging, other components, PCB, etc, maybe $100-$200 maximum). Of course this insane profit margin is only valid once NRE costs ($200k+) are recovered. But some/all ASIC vendors will eventually recover them... so expect ASIC prices to eventually drop massively.

Oh, TSMC is using 300mm wafers. That is good to know.

Edit: Why does it say under one of the (online forms) that it failed the DRC check? (Design Rule Check)

Is that because you did something unusual with the chip that the DRC would fail the automatic checks?

This update is mainly to address the uncertainty that have been surrounding the ASIC scene recently due to the lackluster performance by our competitors. We will be walking you through our process of getting the ASIC fabricated. Unlike our competitors we are a in-house team and everyone is always on the same page.

Another update will address the actual status of our chips as we have obtained word from TSMC whom will offer us weekly updates on their website. All in all, see our arguments below regarding our competitors and wait for weekly updates directly from TSMC.

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Anyhow, any of our numbers, estimates, and shipping date have not changed, just in case somebody got the wrong idea about this update.

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First things first. the following Gallery is our contract with TSMC with pricing and other sensitive information removed. http://imgur.com/a/DnUNm


Some background information on ASIC production process, before tape out, 3 day before uploading GDS, we fill out a MT form with TSMC detailing the ASIC specific information so they may understand what we are doing. The gallery is here http://imgur.com/a/YOLez


to put simply, to create the physical ASIC goes something like this.

sign contract -> submit GDS for review -> mask making -> wafer making -> ship to packaging company -> packaging -> shipping.
Only then can the chips be in your hands or placed on PCB for finalization.

This whole process will take 30-50 days depending on the processor node technology used, mainly due to the increasing in layer number as you go down in processor size. for example, we have 29 layers, and since TSMC is one of the big companies in fabrication, each layer take 1.2 ( normal lot ) day per layer. in addition, accordingly to friedcat, their fab is producing 4 layers every week [odd, but I guess it is possible if fab is small].

This also means while you wait for the wafer(chips) fabrication you can not do anything else, it is usually around this time you make sure you have everything else ready.

a few things to note is,

1. while this wafer making process is going, you can't cancel it, or make adjustments, and if you wish to change anything, you will have to re-run this whole work flow all over again ( the large amount of the NRE upwards of 6 digits in USD is paid when you make the MASK). so anytime, BFL mention they are waiting for chips to come e.g. next week, but if they are still making adjustments, then this is physically impossible. In addition, fabrication company don't do chip packaging, if they are expecting the chips to arrive next week that means the production is already finished and they are probably in the chip packaging company (it is usually this time you find out if your chips work or not. which can also take some time since you'll have to test each of the chips for defects.)

2. the whole chip fabrication is very mathematically predictable based on the number of layers your ASIC has and the speed which the fabrication company can produce a layer. There is no such thing as a fabrication company giving a "fuzzy" date when it comes to when the chips will come from the assembly line. The only number that can vary is the shipping time from the fabrication company to the packaging company, but even that is no more than a few days of difference, depending on the shipping method.

3.a if bASIC made an MPW to start (which is the correct way to save money, but not time). the cost to get large amount of chips during this time is astronomical, however the average size is about 50. It is unheard of for somebody to only produce 2 chips to built a prototype and now no longer have any chips left over to build another prototype.

3.b. Even after testing MWP and everything is fine, it'll take the same amount of time to produce a new MASK ( cost and everything ) then make wafers, which will take another 30 - 50 days, which I suppose is consistent with bASIC's new mid-Jan shipping date, ( but this is optimistic estimate, the regular workflow is about 2 month)

3.c. what we think that happened is bASIC has licensed a SHA256 core, the IP company has already produced demo ASICs that utilizes this core, and did some math on how many core you can placed in the chip to obtain the 14GH/s estimated hashrate, while regular SHA256 and Bitcoin's blockchain hashing algorithm is not very different but it is not something you can compare via simulation without making an actual chip, and if they made an actual chip, even if it doesn't perform up to specifications you can still demonstrate it and be world first.

the conclusion is as follows.

1. If BFL really have chips coming, then they are not making any so-to-speak "clock buffer adjustments", either that or they don't have any chips coming and have not tape-out at all, it is also entirely possible that they have not make the MASK yet either. I guess we will find out on the week of the 11th, in this month hopefully.

2. we believe bASIC has no prototype, or have any chips. Also we at Avalon have also explored the possibility of licensing an IP core, but after some in-house comparison, none of the core on the market is superior to our own, thus we eliminated that option.

Questions, Comments are welcome.

I edited my post to make it more clear: https://bitcointalksearch.org/topic/m.1381594