Topic: ASICMiner BE300S Samples Arrived, <0.2W/G Achieved at Board Level - page 12. (Read 66455 times)

I was on your side and you lost me with this post.  
BTW BFL fully refunded my money after 16 months, but to say BFL is good or okay and AM is bad or terrible will lose most of us.

Just say AM fucked you and you want a refund and I will be back on your side.

Now to this chip I will most likely buy a piece of gear made from it. I will use CrazyGuy or CanaryInTheMine.  I will wait for others to buy it I won't be a Guiana-pig or lab-rat.

But I like new gear.

I think what he meant was, BFL and HashFast (as indicated) were revealed not only as "late" but also as "confirmed scams". I'm no shill for AM, heck novak and I spent a week and some out-of-pocket coin assembling Tubes for hosting and trying to find fixes for their epically-broken stratum implementation, and then rebuilding shelves to fireproof for Prismas (we haven't had any blow out yet). Not impressed. But I do like these chips, it might be a win.

Please recall, however, that this is a thread for discussing BE300. I think what you want is the other thread - the one about compensation and RMAs for existing hardware. Also please note that AM has pretty much always been bad at communication, and that there are likely a few thousand people trying to sell back their Prismas so a bit of patience will probably be necessary.

PMS. indeedy.

On pictures it's clearly visible PMS01...

PMSL 

It's been like 15 minutes in first post. Then replaced.

More interesting is that PMS01 chip is AM design? If so, it looks like friedcat is talented ASIC engineer...

Missed that - anyone an idea why he took it down?

when you put it in black and white i agree with you, those big chips were way too big and relied on exotic cooling, which turned out to be costly, complex, and unreliable.  in the small chips versus big chips experiment i think its now been proven that extremely big chips are too difficult to cool reliably so yes, i agree with you.  but there's still a very wide spectrum of possibilities.  asicminer has gone for a very tiny die with only 6 gh per chip.  if it runs at their claimed, lets say 0.3 watts per gh, thats less than 2 watts per chip.   thats probably much too small to be efficient.  thats quite a bit less than bitfury's old chip (2.5 watts).  i wouldn't be surprised if bitfury's next chip will be more like 20+ gh per chip.  its all about watts per package that can be cooled in a low cost way.

i think the medium sized chips are probably the most efficient way to go.. the chips are still air cooled (with heatsinks and high cfm fans).. but they pack a lot more gh per package which reduces the number of boards that you need for a given gh's, keeps cooling simple, but also keeps the system size manageable.  less board losses, etc.  spondoolies was onto something with their package size and cooling.

FTFY

Not only were some later with a larger die they were scamming people.

AMleak

ah, gotcha, in that case, i concur. 

raskul, I didn't mean per-chip surface area so much as per-miner surface area. It's a lot easier to supply and maintain a handful of 4x4 heatsinks to cool multi-chip blades than it is to supply and maintain a waterblock and radiator for a 400W 2cmx2cm die. That's what I'm saying. When I said "increased surface area decreases cooling requirements" what I meant was increasing the board area over which you have to spread cooling - take the difference between an S1 versus a Sierra board. Similar power draw, but one's spreading it out over a square foot of PCB instead of a square inch of silicon. The AM Blade would run passively cooled with its ~5x8 inch heatsink at 85W, where a Minion requires decent heatpiped CPU coolers to draw the same power from a single postage-stamp area. Not that my opinion is particularly valuable, but I'll pretty much always endorse multi-ASIC designs with simpler heatsinking requirements over things that require complex or cumbersome cooling setups.

Having single ASICs that run about 5GH at 1.2W per chip, one could stack them about as densely as the BE100s on the old AM blades and make a decent machine. It'd run cool, but not terribly space-efficient - about the same as the BE200 chips, I think. Maybe a little better.

i didn't say more difficult to cool, but more cooling required, which would be obvious?

You're both saying the same thing, distributing hashing power over multiple smaller chips increases the surface area / GH = 'easier' to cool. That being said, its not difficult to cool large chips at all, it just means more cost and weight. [First step up is copper base, then copper heatpipes].

i had always thought it the other way around.. the larger the surface area, the more cooling required... you are not spreading that heat from the centre to the edges of a large chip, you are seeing equal heat across the chip - so a bigger chip = increased cooling requirements.

I don't know about a sea of tiny chips, but I'd much rather see a multi-chip high-hashrate design than a single- or few-chip high-hashrate design. Increased surface area decreases cooling requirements, distributed power decreases PCB requirements, and increased modularity increases reliability and repairability. From an owner/hardware-maintainer standpoint, the most problematic machines I've run were the ones with hot single-die setups.

Large dies are very hard to power and cool. Just compare the companies and die sizes and you'll see a very strong corelation.

Late Companies
BFL: Large die
HF: Large die
CT: Large die
KNC: Large die

On time companies
Avalon: Small die
Bitfury: Small die
Asicminer: Small die
Bitmain: Small die
Spondoolies: Medium die

It's pretty clear that the companies that tried big dies has the most delays. I do agree the Asicminer dies could grow quite a bit and still work well.

bitcoin mining chips, with their large number of replicated cells (hash engines) are very good for yield - probably the best possible case that a foundry could wish for, as often they can still find useful and functional chips even if not all the hash engines are operational... whereas if you're making Apple A6 chips, even a single defect is fatal and the chip will be rejected.  you need every single circuit to work and any single defect on the die spoils the entire die, wheres for bitcoin mining, they can cope with some, and perhaps even a lot of defects and still have a useful and valuable asic.  for that reason, its not uncommon for bitcoin asics to have exceptional yield compared to regular asics, thus the yield factor doesnt become as important as the cost of each wafer and the efficiency of the overall design.

that said, as you know, wafers are round, and asics dies are rectangular.. thus the larger the die, the less number of dies fit onto a wafer.. because of wastage around the edges of the wafer where the circle intersects the many rectangles.. and if any part of th rectangular die touches the edge, the die is of course unusable.  asicminer uses very small dies, which should mean they will get less wastage at the edges of the wager and should have more usable dies per wafer.  on the other hand, the edges of each die where they're sliced puts a border around each die, which itself adds some wastage (die streets) and a larger area of the wafer is given over to edges versus usable die area on bigger dies.

i think asicminer uses small dies now because they have always done... whereas there would be less packaging cost, and lower board costs, jf they used larger dies with more hash engines per die.  there's some ineffiencies in using small chips that are not fully optimum.  in bitcoin asics... there are also various efficiencies of using small dies.. in that they might be able to be air cooled without individual heatsinks.. which saves cost and manufacturing time...   however, having each tiny die have its own package could become more costly than having larger dies with fewer packages.   personally, i think that larger dies are the way to go.  i think having tiny dies, thus high numbers of packages and larger boards etc.. adds more points of failure, and more board power losses.. so I'm in favour of larger dies in general.  not necessarily huge ones any longer (as they require exotic cooling, which we've all seen isn't as reliable).

@aerobatic: how much does slicing, packaging and testing contribute to the production cost of Bitcoin ASICs?

And separately, how about the effect of yields on cost?

I would assume that AM has experience now in this field, after 2 generations of chips and battling with problems?!

its the goal of the system designer to minimise the system and maximise the contribution of the silicon to the system.. and asicminer have been good at this.  their recent systems are quite efficient and their new one, with string support, should be even more so  - making most of the cost of the system will be the cost of the silicon.  that silicon needs to be extremely cost efficient on a gh/mm basis (which translates directly to gh/$), especially as so many mining asic suppliers are using the same tsmc foundry and similar process, thus their wafer costs are near identical, so the only differentiator is going to be the silicon efficiency of both power and cost.  ultimately, its gigahashes per wafer that directly affect the cost.