Topic: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013) - page 3. (Read 432965 times)

They didn't give them. Its a student project, and to give credit its a fair analysis and implementation, but useless for mining bitcoins. They did not specify which Spartan-6 development platform they were using (but it certainly wasn't an LX150), and their results were fairly pathetic (3.8MHash/sec, I've done better on an LX9!!). They then went on to try multiple cores (bitfury might be flattered, but its not the approach taken by our commercial LX150 mining boards), and finally a port to the Zedboard, which with 85KLE should have given them a performance in the 100s of MHash/sec, if they did it properly. But rather than giving the performance figures they rabbited on about the Cortex A9 cores and embedded linux.

TL;DR just ignore it. They did a bitcoin miner on a Zedboard. Good for them (nice student project). If you happen to have one lying around then you may want to repeat their work and port the open source miner, but don't expect much return. Or if you want a real challenge, write a scrypt litecoin miner. I've got some code on my github to start you off (shameless plug), then you might look at utilizing the board's SDRAM for additional performance.

PS For some unfathomable reason they decided to run bincoind on their Zedboard A9 linux cores (ie solo mining, WTF???). Maybe so they could back their claim of an "efficient and complete Bitcoin mining system", well IMHO its neither efficient nor complete (OK, no need for a pool if solo mining, but they are never going to mine a block). Who are they kidding (other than their professors )?

I read them, but I didn't really can find any rates for comparing.
Does anybody knows rate and power calculations?

Cheers...

2 students + 2 professor to port already available code

In the current Xilinx Xcell Journal: Issue 84 is an article about "Efficient Bitcoin Miner System Implemented on Zynq SoC" which is also mentioning this project.

The magazin can be downloaded here:
http://www.xilinx.com/publications/archives/xcell/Xcell84.pdf

Hello to all,

Just few questions...
Is there somebody with experience on spartan 6? How much dissipation is allowed with heat-sink and cooler?
Is there some hidden - non documented SYSMON on spartan 6 or any way to read temperature of substrate?  

B.R.
Dex

It's running and giving me 20 MH/s... I wanted to play with that, I did some optimization hinted by Quantus, but well it's mining

In case you're still looking for answers on this, I found Makomk's code (on his git repository, not fpgaminer's) to perform best on my DE0-Nano (EP4CE22 - 22K LE), I'm getting 35MHash/sec at 140MHz (it needs a PSU hack else you'll fry the board). My code is here with links to Makomk's original github (don't use mine as it uses a serial comms driver for my Raspberry PI GPIOs instead of the default JTAG one). You may be able to tweak CONFIG_LOOP_LOG2 to fit a larger core on, or perhaps multicore with a second smaller one.

sure, but it goes in the right direction

Don't get too excited, its just a toy implementation really. I reckon for around 10kHash/sec on an LX150 (possibly a bit more once I get the salsa-mix properly pipelined and I can get the clock speed up a bit).

haha actually pretty awesome that you managed to push scrypt to FPGA.. this line really caught my eyes "A Xilinx LX150 port for ngzhang's Icarus board is in development"

Windows is not discarded, but the logistic is hard (full disclosure: ask my wife to use her laptop, will end up in endless inquisition) but possible.

btw, I'm able to program it with Quartus, but I must after every action, to remove and insert back the usb cable. Like if I call two times jtagconfig, I get an answer but after that, a next jtagconfig will fail. To compile my code on Quartus. I must first search for a device, remove and insert USB and then ask to program the device.. then it works. With the test chain option happens the same..  anyway related to scrypt I sent you a PM that maybe would be great

This comment seems to suggest 5V (why would there be a 5V label on a board if it's PSU is only 3.3V?), but you're probably best waiting for a response from someone on the blog. The only other thing I can think of is multiple devices in the scan chain, but you say it programs OK from within Quartus, so that rules it out. Or maybe the linux drivers are buggy, can you try on a windows box? Anyway grasping at straws here, hope you get it working.

Shameless plug, you could mine litecoin at around 1kHash/sec https://github.com/kramble/FPGA-Litecoin-Miner 

yes, I've got little confused. because the boards arrived without power source. I just read under the eecolor, that it requires 1A, 5V. I just got one with the same voltage and current. But reading the documentation, I've got the impression that it actually needs a 3.3V.. then it would explain this unexpected behavior. I would like to let it mine some other altcoin, like namecoins..

OK, I was just confused by the DE2_115_50MHash_20110601a.sof in your earlier post. Looking closer I can see its detected a EP3C40/EP4CE(30|40) which makes sense for that board (strangely enough I was reading that very article just yesterday!)

Its strange as quartus_stp is clearly reading the device ID off the scan chain, but not managing to successfully complete the programming. Perhaps its a noise or voltage level problem with the jtag header? I can see you've posted on Taylor Killian's blog, so meybe you'll get some help there.

Hi, that's not the DE-115 or even other official dev board.

In may/june I was able to get 4 of these http://www.taylorkillian.com/2013/04/using-fpga-of-eecolor-color3.html for $15/each. I just had time to unpack them, 3 weeks ago, then I ordered two cables (form different ebayers to avoid a problematic batch)..

OK, I that's a full USB-blaster jtag interface. I was thinking of the built-in interface on my DE0-Nano which just needs a standard USB to mini USB cable. Does your DE2-115 board not come with one built in? This seems to indicate that it should do, or do you have some custom board that uses a jtag header?

Hi,
actually I tried a new cable, and I'm still getting the same problem. Both cables are a chinese version like http://www.aliexpress.com/item/USB-Blaster-Rev-C-popular-version-CPLD-download-line-FPGA-download-cable/1125609978.html as operating system I'm using Linux (I was using ubuntu, now fedora), 64 bits.

Hi Kramble,

yup, that's what I believe as well.. I ordered a new one, let's see.. I found some complains about Altera USB Blaster clone cables.. let's wait.. I was just wondering if there were any other step (a.ka udev configuration) to be done..

regards

Vpereira

Just to state the obvious, but have you tried another cable? I had exactly the same problem with my DE0-Nano board (using a springy windup USB cable), and I thought I'd fried the board (I'd been running it at too high a supply current from USB), but it turned out just to be an intermittent cable fault.

Hi, I'm trying to program my board (I'm on Ubuntu 64 bits) with Quartus 13sp1 (i tried as well with 12, same error)

running

quartus_stp -t program-fpga-board.tcl

0) USB-Blaster(Altera) [3-2]
   @1: EP3C40/EP4CE(30|40) (0x020F40DD)

Which USB device would you like to program? 0

Selected USB device: USB-Blaster(Altera) [3-2]

0) DE2_115_50MHash_20110601a.sof
1) fpgaminer.sof

Which SOF would you like to use? 1

Selected SOF file: fpgaminer.sof


Programming ...

Result: Error (213019): Can't scan JTAG chain. Error code 86.
child process exited abnormally

ERROR: Programming failed.


After that I must remove the USB cable, insert it again, then jconfig is able to recognize it. Using Quartus II -> Tools -> Programmer, Im able to download it to my board, however if i try to mine it says that it couldn't find any FPGA with the miner firmware.. any idea?

EDIT:

looks like after 100 times removing and inserting the cable again, it was able to work:

quartus_stp -t program-fpga-board.tcl
0) USB-Blaster(Altera) [3-2]
   @1: EP3C40/EP4CE(30|40) (0x020F40DD)

Which USB device would you like to program? 0

Selected USB device: USB-Blaster(Altera) [3-2]

0) DE2_115_50MHash_20110601a.sof
1) fpgaminer.sof

Which SOF would you like to use? 1

Selected SOF file: fpgaminer.sof

Programming ...
Programming successful!
Info (23030): Evaluation of Tcl script program-fpga-board.tcl was successful
Info: Quartus II 32-bit SignalTap II was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 145 megabytes
    Info: Processing ended: Sat Jul 20 11:13:47 2013
    Info: Elapsed time: 00:00:28
    Info: Total CPU time (on all processors): 00:00:01

but to mine, I'm still not being able to find my FPGA

are they any guides to learning how to build a fpga miner.

I just want to experiment really.