He may have been responding to daisy chain architecture having some limitations, 1 chip's link goes or has a weak link, they all go ... that could be read as chip issue unfortunately by design, even though the thermal design and it's scale might be better than one big chip, the implementation, i.e. reference board design should have taken that into account and provided better routing paths for daisy chain for weak or failing chips, etc.
That of course is a limitation of the SPI setup when using daisy chain.
http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus It can be partly solved by using a segmented master-slave setup but of course adds complexity. With that you just lose a few blocks of chips vs the entire chain. Hmm, also might let one restart the block at different voltages/speeds to try and recover... Is that what AMT is doing with the next-gen boards using several micro-processors?
IMHO, what doesn't help is the chips physical stacking, (SPI interface is top layer, buffer memory layer-2 and cores on bottom layer) That leads to a whole lot of possible noise getting in and interfering with the data stream unless special measures are taken to minimize it and also preferably do some ECC. But hell, if it works it works.