Anyone else starting to get super pumped for September to roll around?
judging with the next estimation difficulty of 66m, 1ghash could get you 0.0075 per daystill good enough
Topic: Swedish ASIC miner company kncminer.com - page 1806. (Read 3049501 times)
still good enough
Anyone else starting to get super pumped for September to roll around?
They consider us a commodity, kinda flaterring. But not a currency 
XBT is the unofficial ISO currency code for Bitcoins.
Yeah, I hate that designation. ISO codes don't control me! BTC it is and shall always be >:Barter Barter!!!
They consider us a commodity, kinda flaterring. But not a currency
XBT is the unofficial ISO currency code for Bitcoins.
Yeah, I hate that designation. ISO codes don't control me! BTC it is and shall always be >:
XBT is the unofficial ISO currency code for Bitcoins.
Yeah, I hate that designation. ISO codes don't control me! BTC it is and shall always be >: I'm a little lost: have KnC demonstrated working prototypes? Proof of design/chip production? Anything other than a case rendering and website for preorders? At the moment, seems as though they have less credibility than BFL - at least they've shipped something.
The case is not rendered.Who runs KNC has a million times more credibility than BFL's people, and Orsoc has shipped plenty.
Next!
KNC chip die size at 900mm2?!!!
There are some numbers for comparison:
Nvidia's mammoth Geforce Titan GK110 chip size is at 550mm2, AMD's flagship Radeon 7970 Tahiti chip size is at 350mm2.
There is something wrong.
from KNC's diagram showing the chip has a 41.2mm x 41.2mm lid. Hashfast made a estimation of 30mm x 30mm size die.
Then why let people guess? Unless KnC considers ASIC size is as secretive as penis size.
Hashfast said that their ASIC size is 18x18mm = 324mm^2.
KNC has said they are huge multiple times
Toasts i tell you
Toasts i tell you
KNC chip die size at 900mm2?!!!
There are some numbers for comparison:
Nvidia's mammoth Geforce Titan GK110 chip size is at 550mm2, AMD's flagship Radeon 7970 Tahiti chip size is at 350mm2.
There is something wrong.
from KNC's diagram showing the chip has a 41.2mm x 41.2mm lid. Hashfast made a estimation of 30mm x 30mm size die.
KNC chip die size at 900mm2?!!!
There are some numbers for comparison:
Nvidia's mammoth Geforce Titan GK110 chip size is at 550mm2, AMD's flagship Radeon 7970 Tahiti chip size is at 350mm2.
There is something wrong.
from KNC's diagram showing the chip has a 41.2mm x 41.2mm lid. Hashfast made a estimation of 30mm x 30mm size die.
It's the size of a toast
KNC chip die size at 900mm2?!!!
There are some numbers for comparison:
Nvidia's mammoth Geforce Titan GK110 chip size is at 550mm2, AMD's flagship Radeon 7970 Tahiti chip size is at 350mm2.
There is something wrong.
KNC chip die size at 900mm2?!!!
There are some numbers for comparison:
Nvidia's mammoth Geforce Titan GK110 chip size is at 550mm2, AMD's flagship Radeon 7970 Tahiti chip size is at 350mm2.
There is something wrong.
KNC chip die size at 900mm2?!!!
There are some numbers for comparison:
Nvidia's mammoth Geforce Titan GK110 chip size is at 550mm2, AMD's flagship Radeon 7970 Tahiti chip size is at 350mm2.
There is something wrong.
KNC chip die size at 900mm2?!!!
There are some numbers for comparison:
Nvidia's mammoth Geforce Titan GK110 chip size is at 550mm2, AMD's flagship Radeon 7970 Tahiti chip size is at 350mm2.
There is something wrong.
Wow. This thread is growing as we're getting closer to the release date. It will probably explode by the time we get to September.
I have no idea what they're actually going to do. I assume they know what they're doing.
I would also think you'd still need to pay for the whole wafer space even if your chip doesn't work, right? So getting rid of defective chips wouldn't actually save them $200, right? I figured it would only save them the cost of the PCB, and possibly add more time to their schedule.
You pay for the devices which pass your test on the tester. Bad yield is a problem of the ASIC vendor, not the their clients. Their yield is usually a well kept secret and not disclosed to others. You can also do binning as I've mentioned previously. The output of the test vectors can identify which part (e.g. which hashing core) has a defect.
A miner ASIC is not different from any other digital ASIC with some redundant logic like I've given examples of previously. Like many other designs it contains logic to generate a lot of coverage internally, uncovered nets can be covered by inserting logic. The output of the test vectors can tell you which hashing core has fault (just like with a multicore CPU as I mentioned earlier). Also this has noting to do with JTAG and nothing to do with functional verification or functional testing. It's to test the fabrication of the ASIC device itself.
Is the word may in your sentence above an indication of that you think this is something they should do, or that you have heard somewhere that they might supply vectors and run test on the tester?
I have no idea what they're actually going to do. I assume they know what they're doing.
I would also think you'd still need to pay for the whole wafer space even if your chip doesn't work, right? So getting rid of defective chips wouldn't actually save them $200, right? I figured it would only save them the cost of the PCB, and possibly add more time to their schedule.
You pay for the devices which pass your test on the tester. Bad yield is a problem of the ASIC vendor, not the their clients. Their yield is usually a well kept secret and not disclosed to others. You can also do binning as I've mentioned previously. The output of the test vectors can identify which part (e.g. which hashing core) has a defect.
A miner ASIC is not different from any other digital ASIC with some redundant logic like I've given examples of previously. Like many other designs it contains logic to generate a lot of coverage internally, uncovered nets can be covered by inserting logic. The output of the test vectors can tell you which hashing core has fault (just like with a multicore CPU as I mentioned earlier). Also this has noting to do with JTAG and nothing to do with functional verification or functional testing. It's to test the fabrication of the ASIC device itself.
The guy arguing is making wild assumptions about the KNCminer chip with few hard facts, so you can pretty much ignore the post and save your popcorn until both units are shipping. Then they can start to debate the technical merits.
KnC will ROI, HalfFast will not.
Sadly, with the recent rate of difficulty increase, it appears that nothing will be able to ROI unless it's currently hashing and doing it right now. And I say this having multiple Jupiters on order...
The guy arguing is making wild assumptions about the KNCminer chip with few hard facts, so you can pretty much ignore the post and save your popcorn until both units are shipping. Then they can start to debate the technical merits.
KnC will ROI, HalfFast will not.
The guy arguing is making wild assumptions about the KNCminer chip with few hard facts, so you can pretty much ignore the post and save your popcorn until both units are shipping. Then they can start to debate the technical merits.
I have no orders with HF or KnC but I will enjoy this as things start to heat up. Summer is over let September kick in!
I love engineering battles!
The guy arguing is making wild assumptions about the KNCminer chip with few hard facts, so you can pretty much ignore the post and save your popcorn until both units are shipping. Then they can start to debate the technical merits.
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