Topic: Swedish ASIC miner company kncminer.com - page 1803. (Read 3049501 times)

In that case I'd like to get an answer for this:
The connector can physically do 250W but it's totally not designed for that. If this is the final board designed to handle 320W, it seems weird to only have one 6-pin 75W PCI-E connector for power?

Not trolling, just curious.

So the single asic chip will have 4 areas with pins under, so it fits perfectly in these 4 places?

The connector can physically do 250W but it's totally not designed for that. If this is the final board designed to handle 320W, it seems weird to only have one 6-pin 75W PCI-E connector for power?

Not trolling, just curious.

KnCminer is finally getting the message that they do not have a finished product. The author of the article used the word "design" instead of "product". I pretty much appreciate they are now using the right language to show what they have accomplished so far.

So these boards are upgradable?  You pull the chip out and put a faster one in down the road?  Or up to four faster smaller ones down the road?

Today we have our PCB’s back from the assembly house. These boards will each contain one ASIC chip and be individually connected to the main controller board. The Chip in the picture below is an FPGA which we are using to emulate the full functionality of the boards.
 
The entire space you can see in the middle of the  DC/DC modules (GE Critical Power DC/DC CONVERTER 0.45-2V 40A SMD)  will be consumed by our ASIC. 
 
We would also like to share some facts about our boards with you.
 
The DC/DC modules we have on our boards are the largest and best quality available from GE Critical Power. Each capable of 40 amps making the max available 320 amps per ASIC
Our PCB laminat is not standard either. It has been given extra thick copper layers and multiple power and ground plains which enable it to more than handle our requirements.
We will be using these boards to fully validate the entire setup. They will consume the same power, make the same noise level, produce the same heat and run the same RTL code. The only difference will be related to hashing.

ASIC PCB Board

We would also like to take this opportunity to explain our design philosophy.
 
Our entire design strategy is based on time to market, We have as you can see over specified the PCB by quite some way, our ASIC will only consume an absolute maximum of 250 watts and we know the PCB can cope with 320  watts. This is the level of design margins we employ.
 
So you can use the following to see how safe our design is.
 
We have used a VERY large package for our die, not because our die is large, but to make sure we can handle the power and heat requirements.
We have used more DC/DC modules than strictly necessary
We have used the most pessimistic/conservative estimates in all of our simulations. Including but not limited to Yield, Performance, Power and Heat 
For example while testing each part of the chain. We have tested our onboard Linux device to make sure it can handle up to 1.2TH ( The controller board also has and expansion for additional linux devices for future upgrade/ second generation)
 
Thanks
KnCMiner Team

Nice PCB, hopefully they can give us an estimated shipping date for the first units very soon. September is only 10 days away, knowing in which week the first units will ship by the first week of September would be a good sign.

its the same pcb for asic. they just put an fpga on there for testing and stuff.

Let's see how much time until someone says "hey that connector can't handle alone 250 watts!!"

...
So the single asic chip will have 4 areas with pins under, so it fits perfectly in these 4 places?

no the asic chip will take up all 4 of those areas.

I don't think that is the same PCB they will use in final product. Just an FPGA friendly version for testing

Let me ask again:

So if I understand correct there will be 4 of these boards connected to a one board (the main PCB) inside the case and each of the smaller boards will have one ASIC chips on it, right?

Then why are there 4 slots for chips per PCB?

Kano, I take it neither has CKOLIVAS?

The chip pictured is only they as reference to overall size as it's a known component.

So if I understand correct there will be 4 of these boards connected to a one board (the main PCB) inside the case and each of the smaller boards will have one ASIC chips on it, right?

Then why are there 4 slots for chips per PCB?

Good news, looks like quality all the way.

Our ASIC package selection has been optimized, allowing the use of a smaller package. The selected package is a 55mm x 55mm HFCBGA package (2046 ball count), optimized for maximum thermal characteristics.