This is the best piece of info in this entire discussion. Unfortunately Fabs almost never release their defect density and yields, unless you are a customer under a Non-Disclosure Agreement. In almost two decades following CPU/IC production I have never willingly seen a fab release this info. Very rarely you can get it leaked from a former employee, but then it is always tainted and uncertain if that person has an axe to grind with his former employer or not. Alternatively, sometimes, you will get vague impressions from the executives during financial disclosures, but never the detailed info you want.
Now, the only thing apparently known about KNC is that the package size is about 3000 mm2. Let's assume I am wrong, would not be the first time, and that they have a relatively small chip for the package size. Say 15-20%. That would be a die size of 450-600 mm2. That would still be BELOW the lowest curve on the above diagram. That's really scary for yields, but not impossible to obtain working product by history. But any customer with a die size that large would have to expect very low yields, and they probably had to sign a waiver from the foundry about guaranteed yield due to "design constraints".
Here are some historical data points for 3rd party fab yield problems with some of the larger GPU dies, for bigger customers:
http://www.geek.com/games/ati-and-nvidia-have-troubling-40nm-yields-from-tsmc-815501/ which were "fixed" a year later:
http://www.dailytech.com/TSMC+Says+40nm+Problems+Resolved+Preparing+28nm+Fab+Production+/article17355.htmhttp://www.eetimes.com/document.asp?doc_id=1261006 which were "fixed" about 10 months later:
http://www.pcmag.com/article2/0,2817,2411985,00.aspNow, a TSMC/UMC is going to work with an AMD/NVidia to improve yields because they are producing 10-100s of millions of chips. For a smaller companies, they will not go to great lengths to help them revise designs and processes to improve yields. You get what you get.
Traditionally GPU dies have been some of the largest dies, with the high-end (low yield) parts topping out around mid-500 mm2 in size. And the parallel structure of a GPU is what most closely resembles the SHA256 ASICs being designed and produced by companies today (Avalon, BFL, KNC, BitFury, etc.). So from a manufacturing standpoint, we can probably infer a lot from large ASIC production issues by looking at issues that GPU manufacturers have had in the past.
The bigger the dies, the lower the yield, the more you have to charge to cover your costs on the wasted dies from a wafer. Therefore it is always good to make your dies as small as possible. Just 10 mm2 per die, when factored over an entire wafer, can mean tens of thousands of dollars in improve yield per wafer.
For comparison, here is a good illustration from the 45 nm days, with Intel - who historically have much higher yields than the rest of the industry (the invest more in their process and refinement).
Again, I hope KNC brings to market a good product, and in a timely fashion. The more competition, the better we all do in terms of up-front pricing for our miners. I just am concerned that we haven't see any substantial data about the processor (number of SHA256 cores, clock frequency, die size, heat production, etc.).
Considering the 10+ million dollars of orders they have had, you would hope they would publish this info to keep their investors/customers happy.
You draw conclusions without knowing the chip structure. You assume will have only one die, when is can have 2,3 or 4.
Only a pedant think they have the absolute truth and the others are fanboys.
You must be the first person who is always right. Although chances are that you just believe.
