Cache is amortized over the number of alus you pack in.
the scratchpad is constructed (as a function of the block and nonce).but 2MB is pretty small. 5bn transistors on a 22nm phi. you can put roughly 2000 of those scratchpads on a single 14 nm die.
Oh goodness, no.
Putting aside for the moment the horrible expense of a 5b transistor chip (you're much better off making 5 1b chips, but that's easy with crypto), the math is still incorrect:
- An SRAM cell holds 1 bit.
- An SRAM cell requires 6 transistors (in the most common design)
- The scratchpad is 2 mega*bytes*.
- There are 8 bits in a byte.
So one scratchpad requires 2*2^20 * 8 * 6 = 100M transistors.
Not counting any area devoted to control, AES, 64 bit ALUs to handle that nasty little multiply in the second part of the iteration, etc., that's at most 50 such scratchpads on a hugely expensive chip.
