Topic: [Archive] BFL trolling museum - page 28. (Read 69365 times)

Originally, BFL_Josh said the ASIC devices were capable of running in ambient temperatures of 32F to 95F.
I take this to mean that at 95F the device will reach its thermal limit and pop. 95F is about 35C.

P.S. Avalons' device is tested to work up to 105F (ambient temperatures).

They don't want to be the company that releases marginally adequate products, and I can respect that decision.

In a QFN package?  With 8 chips on the same small PCB?  Do you have proof of this?  Is there a comparable product out in the wild (8 chips on one small PCB using roughly the same wattage in QFN form)?

6.4w per chip should not be a problem. As usual, they're not telling the truth.

Alright, fair enough.  One could certainly argue that the thermal problems should have been foreseen.  I am no expert, so I couldn't tell you - I can only take someone else's word for it one way or the other.

Someone please point it out for me, Those look like the same photos from awhile ago, I would assume that someone would've gone "LOOK!, ITS BROKEN!"

(you can see the bubbled chip in one of the pictures, I think someone pointed it out.)

Someone please point it out for me, Those look like the same photos from awhile ago, I would assume that someone would've gone "LOOK!, ITS BROKEN!"

Someone please point it out for me, Those look like the same photos from awhile ago, I would assume that someone would've gone "LOOK!, ITS BROKEN!"

They did - it was in the first set of pictures they released showcasing the PCB.

Pictures:  http://bitcoinmagazine.com/butterfly-labs-releases-more-asic-photos/

why aren't they showing us the god damn blown chip then ....:/

We made the decision to go with QFN in December. I can't really talk about our development process itself, but we have gone through extensive design and testing phases... at one point in early December we decided to look at a worst case scenario if the chips were in a really hot environment (you can see the bubbled chip in one of the pictures, I think someone pointed it out.). We paid a company out of California quite a bit of money to run a run of simulations under different scenarios on our boards, as well as if we made changes to various portions of the PCB if we could salvage the QFN package's thermal envelope. We were able to get the thermal loads down about 6C off the current mark, but we were still within single digits of the max temperatures of surrounding components once the heat started to migrate through the ground plane. If someone in a really hot area ran these things, the fan would be on full blast the entire time, and as dust and other detritus collected on the HSF the unit would start to overheat and throttle (or worst case, you'd get bubbled chips). The internal junction temp of our ASICs, if I recall is around 121C, however the MCU and a couple other components are around 100C or less if memory serves and we were butting up against that in some cases, in the 90's.

I've already touched on some of the roadblocks we've had. One of the more annoying ones was the diffraction issue ... for example, at 65nm if you try to make a square shape on a wafer, you can't just make a square shape on the mask, you'll end up with an ellipsis of some sort due to the wavelength of light. So you have to shape the mask to accommodate the wavelength so what ends up on the wafer is a square, though it looks very different on the mask. So you have to go through just about everything, making sure what you want is actually what ends up on the wafer... the delay this caused was not anticipated to the extent it delayed us and since this is a full custom, hand routed chip, basically it had to be gone over by hand from top to bottom.

Another delay we've had to endure is the fact that we have effectively tied the ASIC teams payment to the success of the chip. If the chip were to be a failure they don't get paid... so they have incentive to get it right but that has made them very cautious and slow to approve final masks (This is why we can refund all pre-orders we want and why we have the capital to do what we need to do without a failure putting us in bankruptcy).

Ultimately, it has all boiled down to the incredible complexity of the chip (I mean, look at that beast, it's all black in the shot it's so dense). If the chip were not so complex and so efficient there wouldn't be a heat issue, there wouldn't be the wariness of releasing the mask, etc... This is why I find it patently ridiculous that Tom kept claiming his 90nm sASIC or PnR chip would be 100w, it's ludicrous. Avalons claims are far more reasonable at 400w for their design and is why I haven't given them such a hard time. I think Avalon is going to run into some problems that we've run into, but I don't think they will be anything insurmountable, but I suspect it will delay them a bit while they try to figure out how to mount all the heat sinks or the giant heatsink they are going to need to keep the thing cool, and the board itself has to be massive. Tom was estimating 7 x 9" if I recall for his 16 chip 90nm process... the Avalon is 110nm with at least 80 chips I estimate... though I'm sure the chip footprint is much smaller, we're still talking about a bucket load of chips that all have to be cooled. If their package, and I think they are using QFN, is not letting enough heat out the top they are going to flood their thermal and ground planes with 300w+ of heat and cook everything in sight. We were fighting 60w of heat (granted, on a much smaller surface area) and it was a problem, I can't imagine trying to fight 300w of heat. For their sakes, I hope they have already considered these issues or it's going to be a nasty surprise the first time they turn a unit on and the chips start popping and letting the magic smoke out.

I'm not comfortable with how much information they're still hiding. They claim it's because they don't want the competition to see what they're doing, but that's B.S. if you're truly only weeks away from shipping the completed product.

Given all the commotion, it would be all too easy for them to disclose what they're doing and calm everyone down, but they don't. Suggests to me there's no progress to show.

Not that I'm complaining, but that's my observation.

ftfy


Heat management is not exclusive to "Bitcoin ASICs."  Knowing a certain TDP will be problematic with a certain package and it's consequences to other components isn't rocket science, err, Bitcoin ASIC science.


I'm really getting tired of hearing pedestrian engineering mistakes being attributed to the difficulty of the bitcoin hashing algorithm as implemented in hardware.

...

It's not a scam.  All signs point towards a company inexperienced in producing Bitcoin ASICs ASICs attempting to produce Bitcoin ASICs.  
...

BFL says they have successfully tested their ASIC chip design then, and all is good to go on that front, it's just the chip package that needed some changing.

Because ---- you didn't deliver what I paid you for!
Month after month after month after month nothing but baloney!

No, we haven't been able to test the FCBGA in real life... but FCBGA is basically the best you can get as far as heat transfer goes. I mentioned the internal junction temp of 121C in the post - I want to clarify that 121C is the maximum temp for the internal junctions in the ASIC, not that we ever saw anything near that. Our maximum temps were around 95C I think it was. The ASIC chip itself was perfectly fine under all conditions, it was the heat migration out to the rest of the components that was causing a problem and was due solely to the fact that we could not evacuate enough heat out of the top of the QFN package. Switching to FCBGA almost completely eliminates this issue.

FCBGA is what's used on many 130w - 150w TDP chips and works fine... we are running 6.4w per chip. There won't be any issue at all with heat.

BitPay is the processor, so if you really have a qualm about it you should take it up with them...