Don't worry, I don't take this personally. The more posts from 2112 I read, the more I get the feeling that he is probably a little bit too long out of the real world ASIC business
That portion agrees with my self-assessment.
and if he ever got to know it, then more from an academic point of view.
This doesn't.
By the way, he is not the only one who had strange experiences with Apache (now Ansys) tools and these are only niche tools, which you need for a very small part of the overall design flow (sorry for the CAD monkey terms).
This portion show that you've didn't read my post with understanding. I never used Apache, I quoted Hashfast's CEO.
You have of course to do a design exploration of different variants of hashing cores. And if you want a complete picture then you have to do it in different technologies. But I doubt that you have to tape-out all these variants to get to know, which one is the best and should be used in the final ASIC. If you are an experienced CAD monkey
you can determine which of your variants is the best with high confidence without silicon, at least relatively to each other. Real silicon results will be +/- 15%, maybe +/- 20%, but not more, otherwise you missed something very important during the design phase.
-15% -20% (or any mention of +%) is pure science fiction. The "very important" thing missed by HyperMega (and others) is that coin miner is unlike nearly every digital chip it will be only operated overclocked/undervolted, in the regions where digital model don't apply and one has to use the mixed-signal or analog design flows.
And in any case, finally every working mining ASIC will be a layout based on a replicated highly optimized hashing core, because there is no other efficient way to implement so called multi/many core systems.
If I would do a prototyping run like discussed above (based on a MPW run), then I would try to get as close as possible to the final ASIC with respect to performance, die size and packaging concept to be able to pipe clean the complete miner system design including cooling setup, string regulation concept and so on. That does not exclude that you include different variants of hash cores in the prototype.
Anyway you should keep in mind, that the complete prototyping cycle AFTER you have finished the design will take at least 6 months including packaging, measurements and analysis. That is why almost everybody who has “successfully” brought a miner to market skipped this step.
Yeah, I'm slowly getting the "new way" of selling the ASIC design services. There are no plans for repeat business, it is strictly one-time hit-and-run affair.
Personally, I wonder about why Spondoolies' subcontractor designed POST (Power-On Self Test) circuitry into otherwise quite competent ASIC design. Then Spondoolies' software had to explicitly re-enable hashing cores that only failed POST when cold, but hashed fine when hot. No other vendors made such a mistake.
This got be something related to the contract between Spondoolies' and their vendors, like somebody doing excessive sandbagging to cover their asses. I wish somebody familiar with current practices (and not bound by NDA) could post their SWAG (Scientific Wild-Ass Guess).