Topic: Bitfury: "16nm... sales to public start shortly" - page 13. (Read 108494 times)

Is it just me or has BitFury tacitly admitted to their failure on the 16nm node?

http://bitfury.com/content/4-press/the_bitfury_group_announces_next_step_as_a_digital_asset_platform_company.pdf

That portion agrees with my self-assessment.
This doesn't.

This portion show that you've didn't read my post with understanding. I never used Apache, I quoted Hashfast's CEO.

-15% -20% (or any mention of +%) is pure science fiction. The "very important" thing missed by HyperMega (and others) is that coin miner is unlike nearly every digital chip it will be only operated  overclocked/undervolted, in the regions where digital model don't apply and one has to use the mixed-signal or analog design flows.
Yeah, I'm slowly getting the "new way" of selling the ASIC design services. There are no plans for repeat business, it is strictly one-time hit-and-run affair.

Personally, I wonder about why Spondoolies' subcontractor designed POST (Power-On Self Test) circuitry into otherwise quite competent ASIC design. Then Spondoolies' software had to explicitly re-enable hashing cores that only failed POST when cold, but hashed fine when hot. No other vendors made such a mistake.

This got be something related to the contract between Spondoolies' and their vendors, like somebody doing excessive sandbagging to cover their asses. I wish somebody familiar with current practices (and not bound by NDA) could post their SWAG (Scientific Wild-Ass Guess).

Once again, this is stuff I can bite into.
My 40+ years experience in the IT community was mostly coding and network design/trouble shooting.
0 experience in chip fab.
Last degree was a business admin degree.
So I tend to look at things from a cost/benefit perspective.


"Perfect would be one, which is in your neighbourhood or at least in the same time zone."
Yup

"Sorry, I don't know any IC design service companies in Minnesota."
Didn't expect there would be.

"www.uniquify.com
(did the design for Hastfast)
www.open-silicon.com
(did the design for Cointerra)

Both are located in CA. Probably not the best examples looking at how the stories ended. "

Maybe they learned from their "mistakes".

Another one in US (also CA) is www.esilicon.com

"But in principle I doubt that any of these companies would implement a 0.1 J/GH ASIC for you below $1M for design services (this does not include the mask costs), if they are interested at all."

Big money doesn't scare me. Big money outlays with a high likelyhood of a negative ROI does.

"The reason for this is that there are no low hanging fruits anymore. If you want to be successful with a new BTC ASIC, many custom CAD monkeys have to work really hard, because any competitive ASIC has to be implemented based on custom digital design techniques to reach 0.1 J/GH.
It is easier to reach this target based on 16nm, but probably not impossible in 28/22/20nm. Anyway it would require very high effort, compared to the first ASICs which hit the market in 2013."

Paraphrased: It's a bitch to implement a competitive design in 16nm, and hence, expensive.


Given the $13/chip price (versus $4-$6 that was hoped for and assuming they are ever available for sale to the general public, i.e. sidehack et. al.) this "loosens up" the requirements of initial cost outlay. i.e if a comparable (or enhanced) design could make it to the street for, say, $8-$10 / chip (and a whore-ish attitude to sell them to anyone in any quantity) that sounds or "smells" like a business opportunity to me.

My initial projections of $2M to get 500,000 chips in hand, based on the best information at hand, is/was obviously WAY LOW. But the MSRP of that concept was in the $2-$6 each range. If the MSRP gets bumped up to $8-$10 each, then the requisite increase in initial outlay could be warranted. It'll make reaching the "critical mass" initial funding more difficult, but might not be un-doable.

Maybe I'm over simplifying things here, but if 500,000 chips costs $8 each and one marks them up $1 each that sounds like 12.5% ($500,000) gross. In an E-business sales model most of that drops to the "bottom line" (net) and could be used to "seed" the next project.

Perfect would be one, which is in your neighbourhood or at least in the same time zone.

Sorry, I don't know any IC design service companies in Minnesota.

www.uniquify.com
(did the design for Hastfast)
www.open-silicon.com
(did the design for Cointerra)

Both are located in CA. Probably not the best examples looking at how the stories ended.

Another one in US (also CA) is www.esilicon.com

But in principle I doubt that any of these companies would implement a 0.1 J/GH ASIC for you below $1M for design services (this does not include the mask costs), if they are interested at all.

The reason for this is that there are no low hanging fruits anymore. If you want to be successful with a new BTC ASIC, many custom CAD monkeys have to work really hard, because any competitive ASIC has to be implemented based on custom digital design techniques to reach 0.1 J/GH.
It is easier to reach this target based on 16nm, but probably not impossible in 28/22/20nm. Anyway it would require very high effort, compared to the first ASICs which hit the market in 2013.


You can do nothing with bare die samples, despite you have suitable test prober equipment, which is also not cheap.

Maybe a comprise would be a COB setup (Chip on Board). Here the bare dies are directly wire bonded on a fine pitch PCB.

Don't worry, I don't take this personally. The more posts from 2112 I read, the more I get the feeling that he is probably a little bit too long out of the real world ASIC business and if he ever got to know it, then more from an academic point of view. By the way, he is not the only one who had strange experiences with Apache (now Ansys) tools and these are only niche tools, which you need for a very small part of the overall design flow (sorry for the CAD monkey terms ).

You have of course to do a design exploration of different variants of hashing cores. And if you want a complete picture then you have to do it in different technologies. But I doubt that you have to tape-out all these variants to get to know, which one is the best and should be used in the final ASIC. If you are an experienced CAD monkey you can determine which of your variants is the best with high confidence without silicon, at least relatively to each other. Real silicon results will be +/- 15%, maybe +/- 20%, but not more, otherwise you missed something very important during the design phase.
And in any case, finally every working mining ASIC will be a layout based on a replicated highly optimized hashing core, because there is no other efficient way to implement so called multi/many core systems.

If I would do a prototyping run like discussed above (based on a MPW run), then I would try to get as close as possible to the final ASIC with respect to performance, die size and packaging concept to be able to pipe clean the complete miner system design including cooling setup, string regulation concept and so on. That does not exclude that you include different variants of hash cores in the prototype.

Anyway you should keep in mind, that the complete prototyping cycle AFTER you have finished the design will take at least 6 months including packaging, measurements and analysis. That is why almost everybody who has “successfully” brought a miner to market skipped this step.

Thanks, that's info I (a non-fab chip guy) can sink my teeth into.


Recommendations of companies that have experience in BTC chip design?


Had a hunch that chip fab was a "black art" with few knowledgeable participants.
We cannot support a $500K budget for tools much less the employee expense to operate said tools.


North Central US (North Central Minnesota, near Leech Lake to put a finer point on it).

Considering the ~$1,000 per die prototype expense, the packaging seems cheap.

Is there any advantage to not packaging the prototypes?

In my opinion the same outcomes may be accomplished without being such a traditional forum dick.
You do not have to be nice, but being so pompous and egocentric only serves to be that dick.

It is so over the top it is an obvious wish for control that person is unable to exert in day to day life.

Growing up a bit would be an amazing accomplishment for someone so accomplished.

Smart people do not have to be nice. Truly smart people do not talk down to people in the manner exhibited throughout the last few pages of this thread unless they are spoiled and socially challenged without any respect for the subjects they are discussing.

You only see people take the behaviour to that level on the internet. In day to day life they do not last that long without serious physical security or running a corporation where people are afraid of losing their livelihood. Even then they only keep followers or people who are unable to make their livelihood in another company, never true leaders.

In my opinion showing respect for someone with a perverse need to talk to people in that manner only provokes more of the same. It doesn't matter how much someone may or may not be able to offer, if they have a personal need to satisfy which involves talking down to someone in such a vulgar manner they are more concerned with satisfying their own egocentric requirements than they will ever be with helping you accomplish your goals.

More akin to the villain in a story rather than the hero. A villain which leads you to an edge and pushes you over to your death.

The world is a better place without such regardless of almost any potential contribution. It is one thing to be confident in yourself and abilities, but quite another to speak at / down to someone rather than having a reasonable conversation.

It is a weakness, a personality fault, and an obvious cry for attention.

I learned a long time ago that smart people aren't always nice, and nice people aren't always smart. The important thing in any discussion is the two sides end up understanding each other, and I figure most arguments happen because at least one person doesn't care to try and understand the other side. 2112, just keep doin' what you're doing and I'll try and catch up.

Mr Kashif has also PM'd me a couple times over the last few months, mostly asking if I'll talk to him on Skype and only Skype. When I give him alternative options (the kind with a text log of the conversation) instead he disappears for a month then comes back to ask again. So I don't know what you got out of him but so far all I know is he really likes Skype and VoIP systems but apparently is paranoid about text-based communication?

It takes different kinds of bait to catch different kinds of fish. A touch of snarky-bait convinced eldentyrell to surface his submarine and post a reply after more than a year of underwatersea navigation. Also a salesperson from some fabless boutique made a post.

On smarmy-bait you'll catch fish like Mr. Kashif. Bitfury folks would be crazy to invite him to their office. After exchanging some PM's with him I'm sure that if he somehow had shown up in my company's office the security would escort him out.

It takes a certain appropriate mix of "school smart" with "street smart" to swim in the ASIC waters and not get eaten by sharks.

I'm actually dedicating this post to all of non-engineers who can't understand all that semiconductor industry jargon. For them I wanted to recommend a book by Feng-Hsiung Hsu from 2002 entitled "Behind Deep Blue: Building the Computer that Defeated the World Chess Champion". He was the lead engineer who designed the chip, but he co-authored this book with some professional writer and the result is a page-turning thriller. There are absolutely no equations. Neither engineering nor chess knowledge is required to enjoy this book.

Obviously the actual technical material and example prices are obsolete. But the book will show the reader how to successfully skate the edge between academia and commerce (in case of Hsu it was Cornell and IBM). His opinion about using commercial "layout services" for repetitive ASICs in my opinion still stands as valid.

http://www.amazon.com/Behind-Deep-Blue-Building-Computer/dp/0691090653/

Use the above link if you are the person who likes to pay and be treated with respect.

http://www.worldcat.org/title/behind-deep-blue-building-the-computer-that-defeated-the-world-chess-champion/oclc/50582855

Use the above link if you are OK with reading this book for a price of smile and a wink to your friendly neighborhood librarian.

I'd assume Hyper is talking about final real estate once some ideas have been tried and weeded through no?

Aside from that, as always seems you do bring up points we can agree on, in this case the necessity of doing more than just sims. Just ask BFL, Cointerra, Bitmine.ch as well as others how well that works (going straight from sims/FPGA work directly onto full silicon with pre-order promised delivered-by date(s)) on the horizon. Despite how the expense looks to accounting and the time required as always abhorrent to MArketing, the need to test ideas with physical silicon cannot be bypassed. Running an assload of smaller (and cheaper) dies gives a chance to test different cell layouts  for several different functions to find best and most cost effective of breed to then start integrating together for proto-round-2.

Just like when using SPICE, one cannot always trust what the models say. It's the minutiae of real-world circuitry that never fails to surprise ya from time to time.

I'm glad you were able to catch and correct my error. Admittedly I'm nor really familiar with the merchant terms for one-off designs. I always worked either through academia or with the long-term projects that involved purchasing options for masks and wafers.

WIth SHA256D miner isn't any issue of secrecy or intellectual property. Getting into partnership with some academic institution would not be problem at all. That was what Bitfury did with their first chips. Here's a quick example of a subject for a master thesis or a post-doc paper:

Comparison of combinatorial constant-propagation gains versus passive transmission loses through varying unroll factor in digital circuits with high toggle ratio.

That would be about 75% to 90% of work required to optimize a Bitcoin miner ASIC. For particular example Bitfury used unroll factor 2 in his original chip.

This is a perfect example of daft thinking of a CAD monkey. No sane hardware engineer would waste that valuable real estate (50 plots of 3 square millimeters each) to fill it out with identical unrolled cores and try to commercially mine with them. The sane engineer would fill those 3 sq.mm with as many different interesting designs as he/she could think of and then compare simulated results with actual results to gauge the accuracy of the toolchain. That is the whole point of prototyping.

I understand that some people find "CAD monkey" term offensive. But such proposal as above is equally offensive to the normal hardware engineers. That is why https://en.wikipedia.org/wiki/Code_monkey epithet was invented to quickly distinguish a narrow subset of programmers.

This never happens to students or faculty at non-profit schools. It does happen in for-profit schools or maybe at non-profits when administrative staff gets involved in theft or unauthorized resale. In normal schools the https://en.wikipedia.org/wiki/Academic_freedom and https://en.wikipedia.org/wiki/Scientific_freedom will easily trump the short term commercial concerns.
 
I worked for a while for EDA vendor and I start sensing a sales-critter. I'm the last person to try to blame the sales person for trying to earn the commission. In fact I'm still grateful for being invited the celebratory party of one salesman who with single sale funded (pre-paid) college education of two of his kids.

I also remember particular post trade-show dinner party (in Anaheim,CA or Las Vegas,NV) with various EDA industry bigwigs. One thing I remembered was one founder being asked how he got money to start up. His story was that out of school he was reselling used office furniture.  One time they bid several k$ for a closed office of some major US automotive concern (Ford? can't recall anymore). It turned out that the cabinets were filled with Ford's(?) internal paperwork related to hard-to-fix warranty repair problems. They actually successfully blackmailed Ford(?) into buying those cabinets back for some 1M$.

Why I'm retelling this story? People need to learn how to bargain with EDA vendors. Here's a quick example:


Cheaply buy out of the bankruptcy the intellectual property that went through that Apache Redhawk simulation with gross errors. Then talk to Ansys https://www.apache-da.com/ to fund a research grant that would establish the reasons for such large errors and ways to correct their products. It is not much of business idea but it is an idea of how to not only get expensive EDA tool for free but also get funding/grant for its use at a research university.

Just notice your post Sidehack. Nice to see someone thinking laterally but why not make this into a separate thread where it might attract more views and possibly more inputs to your questions?

For my two cents worth, forget about 20nm, it never delivered what it promised but good old 28nm is cheap and stable and there's plenty of design expertise at reasonable cost. As a quick answer to your question, to effectively create a system to give you 1 million 28nm production asic's at around twice the die size as Bitfury's 16nm (40 mm² as against 25 mm² I'm guessing) running at around 100Gh/sec at 10 watts at a 'sweet spot' would take about US$ 7 million, or $7 per chip. Of that around $4 million is for the actual packaged devices, the other $3 million is NRE and design fees. Making 2 million would work out at $5.50 per device. Hope this helps.

Hypermega: Thank you for a very useful reply to Sidehacks questions vs the snarkasim from 2112. Needing to ask questions about things outside of ones core competency is not a bad thing and should be met with better than Ivory Tower attitude.

That is definitely not true.  I have a chip I designed and fabbed through Europractice sitting in front of me right now and neither I nor my company have any connection to Europe.

For a while TSMC would not let them quote US customers, but that restriction was for that one fab only and it has since been removed.  The only thing Europe-only is the academic discounts.

Europractice's IMEC team in Belgium (the ones who do UMC+TSMC tapeouts, but not GF) are absolutely top-notch, outstanding people.

Yes, bare silicon dies in gel-pak.

But if you go for a standard package, prototype packaging service is also available:
http://www.europractice-ic.com/prototyping_packaging.php

Don't be scared, in volume production the packaging per sample is much cheaper.


Yes, but this is not much for a mining ASIC even in 22nm. I guess it should equate to about 10 ... 15 unrolled hash cores, because this 22nm GF node is only a 80% shrink of the GF 28nm node, not a true 50% shrink like other 20nm nodes. But therefore the 22nm masks cost only a little bit more than a 28nm mask set.


You have the choice

www.synopsys.com
www.cadence.com
www.mentor.com

You need a bunch of these tools and people, who know how to use them.

In general EDA tools for advanced nodes are very expensive ("big problem, small market"). A complete full+semi custom tool-set for a small design team will cost you at least $500k per year.
And yes, Universities have these tools almost for free, but for strictly non-commercial use. As soon as you want to design something, which could be commercialized directly or indirectly it is illegal to use University licenses for it. If something like this would be discovered by the EDA vendors, you and the University would have huge problem.


If you like to get your feeds in the water here, it would be better to cooperate with a IC design service company at least for the first project. You bring the chip concept and architecture, they help you to design, manufacture, package and test it.
From my point of view, it is almost impossible to build up the required competences from scratch, despite you hire some experienced IC designers in your company.
Where is your company located?

Some ol' some ol'

... Announce an unrealistic timeline ... OR ... promise heaven on earth (tomorrow)  
... Stir the PR pod pood  
... Become very silent  
... release (if ever) with massive delays  

All because of (EVIL) world happening.  

Just wait and see  

    one4many

Does anyone have any updates from bitfury regarding their chips?

Fair enough, that's just the descriptor language I know exists and we touched on it a bit in a class some years back. I'm not really sure who I'll have to talk to about admissions, but I'll be on campus one day this week to get the ball rolling. I've already put in six years there (ending six years ago), where I ran out of money about a semester shy of completing degrees in Computer Science, Computer Engineering and Electrical engineering with minors in math and writing (and about half a physics minor). So there's a lot I know something about but nothing I know everything about, and chip design innards (or the languages and toolchains required) is something I hadn't looked at at all.

I don't really have a 40-hour week to sit down and do anything. I'm already at work about 65 hours a week as it is, not counting when I take work home, and sometime in there I have to handle meals and household stuff. Maybe sometime in June, if I'm between manufacturing batches, I'll have time to hammer on it.

This looks like you want to have career as a CAD monkey at a defense contractor. In the USA VHDL is mostly used by those who are paid by Department of Defense (VHDL being an offshoot of Ada, also sponsored by DoD). The civilian industry mostly uses Verilog.

Anyways, learning VHDL or any other hardware description language emphatically isn't learning foundations. This is just a front end, one of many ways of inputting the design into the design workflow. If you have solid foundations, you could pick up VHDL, Verilog, SystemC or any other language in about a week or two of full time work (8hrs/day 5days/week). I know I did just that at my first job. Within first month I started filling bugs against the VHDL compiler (they were quite immature then.)

Overall, learning such a shallow stuff like would be a waste of time and money at a college for somebody who is already working and not looking to extend his childhood. To make the college costs worthwhile you'll need to make their enrollment/intake people really work for you. Here's how to do it properly (I'm assuming that your educational goal is to learn how to design a really good Bitcoin mining ASIC).

Don't mention Bitcoin. Mention the following problem: I have a 28nm ASIC in which the critical path is in the expression temp1 := h + S1 + ch + k(i) + w(i), all values being 32-bit registers. This ASIC works at about 300MHz. On the other hand I know that Intel CPU could execute instructions like mov eax,[ebx+4*esi+offset] at a rate of about 3GHz when still using about 100nm process (Pentium 4 a.k.a. Netburst). There are only two visible additions in the Intel instruction, but more are hidden in the segmentation/paging/caching hardware. I don't want to compete with Intel, I just want to learn how to make my little ASIC run at a real competitive speed. Can your school teach me something that would help me achieve this goal?

I don't know the admission process in your school, is it just a single administrative person or are you going to face an admission committee consisting of a mix of administrative and teaching faculty people? You may also want to visit your school on some "open days" and talk to the prospective professors.

Your original idea (asking for VHDL course) looks exactly like you were trying to fit yourself into some job posting from a defense contractor. It is your life and I can't tell you what to do with it. But in my opinion focusing on minutia is a wrong way to pursue education.