Topic: Bitfury: "16nm... sales to public start shortly" - page 14. (Read 108494 times)

If I'm thinking right, VHDL would get me FPGA design, which is probably a good place to start making sure I at least know how to do the basics right with some real-world implementation. It wouldn't directly help me build anything ASIC but it'd be a start. I'd like to have more of a foundation to build on.

And pray tell, how would learning VHDL help with developing efficient ASIC mining chip? How that thought popped in your mind?

Or we could maybe invoice Bitfury for shilling services in their thread?

You won't like my answer, but I have to reiterate what I wrote in response to sidehack. You can't afford to ask stupid questions. If you behave like a time-wasting crank, people will treat you like a crank or crackpot. Both MOSIS and Europractice don't have funds to employ salesforce that could tolerate such inquiries. It is presumed that the prospective customer of theirs is sufficiently intellectually inquisitive to read information on their websites.

Europractice serves only European countries plus some culturally related territories, like ex-Euro colonies or ex-USSR. PlanetCrypto is based in US, so you will only qualify for MOSIS. I referred to Europractice partly because of my background and partly because more of the Europractice's site is available for non-members, before signing off the NDA.

I still live in the town where I went to college (Rolla is home to one of the best engineering universities in the central US), in part because I ran out of money before finishing school (y'all know how much I hate borrowing). If some plans I have in place right now work out, I should be able to finally get back in this fall and finish up in one or two semesters part-time. I'll see what classes they have on VHDL when I'm talking to enrollment folks this coming week.

Also, possible this line of discussion should shift over to the Community Miner thread, since - and yes I know it's my fault - we're tangented pretty far off topic now.

Since it's obvious I couldn't find my ass with a map in the chip fab world, how about clarifying a couple of things:


"unpackaged" means the bare die with no carrier? right?


"3mm²" is the die size?

What is "... the required CAD/toolchain" to design (tape out?) something like sidehack was proposing?

We, as a company, have a couple of other chip concepts outside the crypto currency world.
If the cost of the S/W isn't to prohibitive and we knew what we were looking for/pricing we might spring for it.

Thanks in advance.

Real, no bullshit, prices from slightly out-of-date Europractice access to GlobalFoundries 22nm process:

50 prototype dies, unpackaged, untested

48,000EUR for up to 3mm² plus 16,000EUR per each additional mm².

I'm not up to speed, but by my understanding is that access through MOSIS (sidehack is based in the USA) is both slightly cheaper and has somewhat more frequent shuttle runs.

A young, personable individual could do the tape out for free by pretending to audition some EE courses in some local (US or EU) school that has the required CAD/toolchain available in the student's labs. I remember from my student days several groups of people that manufactured prototypes on the side while taking courses. The only time my school objected/prosecuted was when some lamers actually physically took the test equipment out of the lab (in effect stealing). Many people overbooked the computer lab time in ridiculous amounts to run side consulting jobs.

Good luck to you, sidehack, personally.

Thanks for the advice. Several things there (and in previous replies) that I hadn't considered. I now know more than I did, so thanks.

I only have a conceptual knowledge of semiconductor design, no practical experience inside an IC package or, to be honest, even FPGA design. Most of my job is board-level design and... well, actually the bulk of my job right now is board-level manufacture of the things I've designed. Guess I'll have some reading to do and other smart people to talk with.

And hopefully someone someday gets back about Bitfury chips.

I think it is possible, even fairly easily, without big money outlay. You just need to find somebody familiar with the proper design flow: mixed signal, analog or high-power. Mining chip designed through a run-of-the-mill low-power digital design flow will be rather inefficient because such they assume too low tolerable error rates and too low internal temperatures and switching noise levels.

You'll be best served not by doing standard merchant-commercial fabrication/production but a prototype/research/educational fabrication through MOSIS or Europractice. (for their first chip Bitfury partnered with some small Polish research institution to be eligible for Europractice prices.) Therefore you can summarily ignore all price quotes from this forum, because they were standard merchant terms.

I'm familiar with the relevant design flow, but my experience and my tools are badly out of date for the modern deep-submicron design flows and tools. I also don't want to be like that Boxer horse in Orwell's Animal Farm,  I know that the sweat capital is nearly worthless in semiconductor design and manufacturing. I'm not an expert, but I know the rules of the game well enough to avoid gallant and valiant efforts that are guaranteed failures.

The other handicap you will be facing is that the Bitcoin mining chip design field is unfortunately mostly populated with crackpot wannabes with less than zero experience. How one could get less than zero experience? There are apparently many fraudulent educational institutions offering "chip level repairing" courses. Please google the the term, I don't want to give explicit URL links to some of the "Expert Laptop Repair Training Colleges". So when you are going to contact the actual practitioners in the ASIC field be aware that they were probably already contacted several times by various crackpots. You'll have to be able to show from the start that you did your homework and have some understanding of the reality, not just the bullshit from the sales brochures. You can't afford to ask stupid questions. Make sure that the questions you ask are sane. Don't ask ASIC designer for a chip in QFN package, because you make yourself look like a prospective car buyer that asks "can I get it in darker shade of grey to match my poodle?"

I'll put my money on sidehack 

If I was looking for a slick salesman to make me empty promises, I wouldn't be asking someone whose opinion and technical expertise I trust. I'm not looking for a guaranteed win at anything. I'm asking if something could be possible and what it might cost to pull off. If you say it can't be done, I'll drop it. If you say it might be possible but not worth the money, I'll drop it. If you think there's a chance it's possible with the right people working on it, maybe I'll start looking for those right people. I don't want salesmen and I don't want monkeys.

The difference between me and someone who gambles on horse races is, I hate gambling and would rather be the horse. Sorry if that freaks you out.

Yes, exactly this is your problem: you want to have a guaranteed win at horse-races without investing in horse breeding and having to smell the horse shit.

There's plenty of silver bullet salesmen in the computer industry that will promise you exactly anything that you'll imagine, with no effort, just send them check/coins. Any CAD monkey can drop a SHA256D into a simulator and come up with ballpark figures for a slapdash standard-cell design: Cointerra and Hashfast did just that.

Only in your opinion "shouldn't be too difficult a question". Any serious professional will tell you that it is a non-trivial question.

Basically, you are looking for a slick salesman who will tell you exactly what you like to hear and sprinkle the sales spiel with some technobabble.

Youtube has several comedy videos like that, but they sell turboencabulators to wanna-be motorists.

Edit: Oh, and again a reminder: please don't take every "you" personally. I'm not really writing to "you-sidehack", but to "y'all, youse who support sidehack and other community miner projects".

Right now? Nothing. Not a cent. I could make time, but I currently have no money. Still working on that part. I just want to know if folks who know more than I do think it's possible, and if it is what it might cost to achieve. You're doing a really good job of avoiding what shouldn't be too difficult a question. I know it's going to be an assload of dollars. But comparing to $13 per ASIC, what are we looking at?

OK, so you are trying to fool yourself.

This is a gambler's approach to design: state the target and then keep shooting until you hit the target or run out of money/ammunition.

You've posted earlier:
Please re-read the book that told the story. This time focus on how much money they had to complete the project, what was their profit/loss model, both for vendor (Lockheed) and customer (US Government). Also analyze when was they key milestone: go/no-go for mass production and what was the percentage of NRE spent before that milestone, that is before they knew if their plane could fly.

Getting back to the mining chip: how much money+time+effort would you/could you spent on simulation of possible designs?

What I'm asking about is the expected cost of one chip assuming the design works and reaches mass production. I know the NRE cost is going to be a varying factor not just because NRE is highly variable but because it'd be a fixed initial cost divided amongst an unknown quantity of individual chips. It's not that I don't understand or am trying to fool everyone. I want an idea of the forest, not individual trees.

So, to be more precise than I at first assumed I would have to be to make the question clear to intelligent people seeking to assist rather than get into semantic arguments - let's say the goal is to design a 20nm ASIC that gets 0.1J/GH somewhere in its operating range; could be bottom clock. Give it about 10W expected power dissipation, fairly standard QFN package. Does someone who knows more about semiconductor design think that's possible? If so, assuming we want to produce 1 million ASICs, what would be an expected TOTAL COST combining production costs and NRE, and what would be expected purely for production costs?

Here's the proof. I tried talking to them about it and asked if I could give them a visit and the last mail I got from them was that they'll let me know. And till now there's no progress or any response from them.

You are using the word "cost" incorrectly. The "cost" in the semiconductor manufacturing industry has two parts:

1) https://en.wikipedia.org/wiki/Non-recurring_engineering
2) production costs

I don't know if you are trying to fool yourself or really don't understand the difference.

Only fools or ruthless salesmen or CAD monkeys would claim that total 28nm NRE costs are lower than total 20-14nm NRE costs. This relation may be true for just some step of NRE, like mask-making. The actual proper "NRE design" (conceptual, architectural, simulation and parameter optimization) do not depend on the fabrication node but on the thoroughness of the design.

Okay. Well I know it's possible to see below 0.2J/GH on 28nm because two or three outfits have done it. From what I understand, 16nm still pulls from something 20nm which actually limits the effective gains from further shrinkage. If it's possible to get about 0.1J/GH out of a more mature (and likely much more cost-effective) process like 20nm, it might be possible to build a compromise miner, with (compared to 16nm) low initial cost and moderate long-term operating cost. Proportionally there's a huge difference between 0.1 and 0.07 but if the 0.1 costs about 1/2 to 1/3 the 0.07 it could still come out ahead, like we're seeing with cheap S7 threatening the viability of higher-cost more-efficient chips.

I don't know. The last time I had looked at the actual CMOS transistor models was for BSIM3->BSIM4 transition which only covers processes down to 23/28nm . Edit: I looked at http://www-device.eecs.berkeley.edu/bsim/?page=BSIM4_Arc , this was year 2000. Further work all the way to 2013 extended the coverage to the 20/22nm processes.

My hunch is that the performance of the mining chips could be greatly improved by using a design flow that actually matches the requirements of the mining chip (huge error tolerance margins, ultra deep pipelining) as opposed to the design flows that are the most commonly used on the fringes of the ASIC industry that deal with hit-and-run customers. And that is regardless of the process node and the feature sizes.

It isn't money that prevents the actual knowledgeable people and companies from working with the coin mining vendors. It is something else, but I don't know what.

Say, question. Do you think it's possible for a 0.1J/GH-order chip to be manufactured on 20/22nm node, and at what cost compared to 14/16nm?

This is an example of grammatically correct semantic nonsense.

At "tape-out" the quantity of manufactured chips is zero. At "tape-out" the chip only exist as a "blueprint". It is conceivable that the total cost to tape-out will be zero or nearly zero, if the chip designer can use existing licenses and resources to design the mining chip.

This is an example of salesman bullshit or more precisely somebody's believing and repeating salesman's bullshit.

How do new productions lines come online and get calibrated? By manufacturing super-complex secret designs of Tier-1 customers? No, they are calibrated by manufacturing waferfulls of repeated testing structures for which the fab has a complete detailed precise models to be able to test and calibrate the production line. After testing those test chips are simply scrapped.

Note that in a mining chip is much closer to the fabrication test structure than the typical highly complex chip from a large customer. Therefore mining chips could be profitably manufactured on the production line that is not yet calibrated enough to profitably manufacture very complex designs.

I stress "in theory" because for some reason none of the mining chip designers seems to be able to enter a proper technological partnership with any of the fabricators. This isn't an issue of money, because from my past experience I know of no-budget student projects that had in effect priority access to the new fabrication processes only on the condition of mutual sharing of the design and test data.

If not money, then what is the obstacle? I don't know. Certainly not intellectual property, because SHA256D miner is banal and trivial in the scale of the things that nowadays get manufactured in CMOS.

My guesses go towards some non-technical issue related to the psychology of the mining chips vendors/designers.