Topic: Bitfury: "16nm... sales to public start shortly" - page 31. (Read 108494 times)

It's not the case with Bitfury chips now that they have the separate comm multiplexer (nor BE100/BE200), but most mining chips from the last couple years (everything Bitmain and Avalon at least) had chained comms so one chip acted as a relay for the next. In that case, even with a regular VRM design you could still kill a whole board with the loss of one part. You could still have partial functionality on, say, an S1 if you lost a chip (or regulator) in the middle, as the ones before it would still hash, but your efficiency would be worse since the rest of the chips are actually still drawing power. I really do like string design but the lack of single-fault-tolerance has always been annoying.

The Prisma had a separate FET on each node as a current shunt, because if one chip dropped out the rest of the board was unaffected as far as signal goes - so the FET would kick on and draw one ASIC's worth of current, keeping all the nodes balanced for power and continue operating. Good idea in theory, but I would guess that's what caused some of their fires.

Guess I'm "cornfused"
And your post is a learning/educational experience and a Homer Simpson moment for me. Doh!
I was thinking that the strings of chips would be, for lack of better words, wired up in parallel (regarding Vcore) versus in series.
Strings in series makes a buttload more sense from a simplicity standpoint (if nothing else component count) but loses the redundancy (or fault tolerance) of chips in parallel.

I come from a military background where things are grossly over engineered AND where cost is no object, so I think and engineer things in terms of continued operation with reduced capabilities.
i.e. everything is mission critical.
Obviously BTC mining doesn't exhibit that criteria.
It also explains why I have a box full of dead BM hash boards.

Thanks for the brain working.

I assumed he meant that many chips wide, where the current does multiply. The wider a string, the more stable it's going to be as any changes in current demand (which then affect voltage) in one chip will be buffered out by the remaining chips in the node, so you really don't want to run a single-wide string if you don't have to.

 Current would be the SAME for a "string" of any number of chips (not counting I2R losses in the power distribution traces and such) - just have to run the voltage higher.
 So a buck for 4 chips in a string would still be just under 40A but would be supplying about 2.32 volts

 

Concur 99.9%.
I was referencing some of our early tests with Novec 7100 and the S3 boards (vid here: https://www.youtube.com/watch?v=gcb9TyQP5ZA ) regarding what it takes to boil 7100. Ambient during the our vid is 70F-80F. and is probably similar to Ambient in the BF vids. In operation, the tank was definitely warm to the touch. Board separation clearance was ~2mm (.006 inches) (i.e. chip surface to spacer plate distance). We fabricated spacer plates out of polycarbonate to minimize the amount of Novec required in the tank. Tank ran at 1 bar (1 atmosphere, 0 relative pressure), so not a pressurized system. Minimizing the amount of fluid contacting the chip/board promoted convection flow (along with the "sparkiling bubbles"). We experimented with clearances down to 1mm, and it worked. Just wasn't comfortable with that little clearance. Am familiar with Alex's Data Tank design. Didn't know there was that much clearance, never thought to look. We also played around with and developed blending tables for the various Novec fluids in an attempt to "dial in" the boiling point for a particular application.

"... is near ambient temp hence the lack of phase-change seen." Raising Ambient would expedite boiling and the converse is also true. Most of the heat removal, in 2-phase, is due to phase change and not in the warming of the fluid to the boiling point (unless of course there is a HUGE delta T between fluid temp and boiling point, but that effect will be short lived as the fluid comes up to temp). The fact that the fluid in the BF vid isn't boiling tends to indicate the chip surface hasn't reached the boiling point of the fluid, whatever it was, and am assuming it was a Novec fluid. Cuz' the Data Tank used by BF, at least initially, exclusively used the 3M product. The fluid in the BF vid, were I to hazard a guess, would be one of 7100's bigger brothers: 7300, 7400, or 7600. This is the difference between immersion cooling, say using an oil which never undergoes a phase change and 2 phase immersion cooling using an engineered/calibrated boiling point fluid which does. Heat removal and consequently power density are dramatically better when comparing immersion versus 2-phase immersion owing to Novec's latent heat of vaporization curve.

Concur
"That is provided the non-insulated data tanks don't already have enough outside surface area to keep the Novec below its boiling point. Doubt that is the case." Aluminum tanks dissipate/leak more heat into the surrounding space than, say, polycarbonate. Or better yet, an insulated polycarbonate container/tank. This is not desirable in 2-phase. As part of the design is to convey the heat away to a heat management system and not into the local area.

Sorry about the rant, I'll shutup now.

Just a little niggle on
"Non boiling fluid provides little convection fluid flow, thereby leaving hot fluid on/near the surface of the chip. And even then, the fluid didn't boil."

In a fairly open system yes.

In the vids BF shows it's a safe bet that the tank of Novec is near ambient temp hence the lack of phase-change seen. Still pretty impressive as ja that shows that the power the chip is dissipating remains rather low.

In a densely packed system with 1-2 cm between the boards like BF's data tanks have thermal siphon effects kick in that will created a surprising amount of flow over the boards & chips. With Novec's very low viscosity that should translate into a pretty decent amount of flow circulating over the boards and back down the sides of the tanks. Once the whole tank of fluid gets near the boiling point then it should get quite lively in the tanks.

That is provided the non-insulated data tanks don't already have enough outside surface area to keep the Novec below its boiling point. Doubt that is the case. If it is they'll just pack in more chips

At 0.15W/GH I'd expect to see in the neighborhood of 140GH at about 20W per ASIC (which is a f**kload of power to suck out of about an 8x8mm package). At low voltage that's a lot more current than I want to see, and yeah I wouldn't do a two-chip node with fewer than 3 phases (and probably 4) on the buck. Thing is, if I want to dissipate no more than 250W per board that's only 12 ASICs for 1.7TH. So now clock it down to 0.06W/GH and you're at about 500GH and you're pulling 30W through your four-phase buck. But if I cap it to more like 0.11W/GH now I'm good for 24 ASICs at 100GH/11W each (and doable with a beefy 2-phase buck) and a top-end of 2.4TH, with a bottom-end of about 1TH and still making decent utilization of my power systems by drawing about 60W. Sure it costs a little more in chips (the primary cost of any design) but my non-ASIC parts cost is halved, overall complexity is reduced, and the factors that really matter for overall longevity (something all miners should require though no manufacturer prioritizes it) - per-chip power dissipation is reduced, top-end and bottom-end hashrates are increased, and average efficiency is better.

I missed ya'll. Good to communicate, again, with individuals with more than 4 active neurons.
That came out all wrong, but I think you get my meaning.

"Opinions are like butts, everybody's got one and they all stink."
So here's the logic behind my stench:

It's obvious, any implementation is going to require logic level shifting. Cuz' comms to/from the chip are likely to be at 1.8V (or higher 2.5V, 3.3V, or dare I put forth 5V). So that complexity needs to be included in any design.

In vid part 1 (https://www.youtube.com/watch?v=3zPpj1JYw38) he's demo'ing @ Vcore of .378V pulling ~6.0A which equals ~38GH/s per chip with efficiency @ .062W/GH/s.
COLD. A reasonable expectation is current draw will increase as the chip heats up, How much, no clue.
While not an easy 10A single phase buck design, it's doable and been done before. Heatsink optional.
My .06 thought was mirroring his demo. For an exclusively air cooled design I'd consider dropping that to .045 - .050. (buck efficiencies may drop horribly??).
That'd put it back to compac hash rates but with significantly better overall efficiencies.

vid 2, heatsink required.

Vid 3 where he "cranks it up" the heatsink is replaced with immersion cooling. Although the chip, conspicuously, is NOT boiling the Novec fluid. So it ain't getting THAT hot. And is probably still heatsink'able. For comparison Intel CPU's surface temperature in Novec run ~160F in 7100. And they boil like water on the stove. 3M (Phil Tuma) has vids on youtube showing this.

Novec 7000 boils @ 34C (93.2F), Novec 7100 boils @ 61C (141.8F), Novec 7200 boils @ 76C (168.8F), Novec 7300 boils @ 98C (208.4F)

The fact that the fluid is not boiling probably indicates poor heat transfer into the fluid (cuz' it's not hot enough to cause the fluid to change state) i.e. it can't contribute enough energy to rise above the latent heat of vaporization curve. Contributing to my belief that even at that Vcore/clock rate/current draw it's still heatsink'able and doesn't require immersion cooling to survive. Is it gonna' get hot, HELL YES. Does it require esoteric cooling, don't think so. Non boiling fluid provides little convection fluid flow, thereby leaving hot fluid on/near the surface of the chip. And even then, the fluid didn't boil.

The buck to drive it is another potential bone of contention. Cuz' it's drawing just under 40A (38.8A) @ a Vcore of ~.580V PER CHIP. Imagine the current draw of a string of 3 or 4 chips. Similar to the current draw that'll start a car (albeit at a higher V). Unless somebody knows of some magic I'm not aware of, that's probably a multiphase buck. Probably 4, 5, or 6 phases at least for dependability and longevity. Each supplying 10A+. These are a bitch to design, increase component cost, and copper trace content/width/cost/board real estate. All in all, would us immersion cooling guys like to see it, YUP. Matter of fact why not drive it to 60A  . Is it the market segment GS is trying to service, HELL NO 

Hence my upper limit cap of .15W/GH/s for this project.

Nuff said, time to lurk.

Does anyone here have an idea for when we can have our hands on the new miners or the chips. It's march now and I have my fingers crossed. any rumors or leads, if anyone has please share it.

Being able to get an appreciable hashrate at 0.06 and not catch on fire at 0.15 will be difficult. I mean that's going to be drawing a lot of current, and making a lot of heat, per chip. The range I'm building for is about 0.07-0.12 like Phil said. Also hey, PlanetCrypto. Long time no see.

  I respect that range pick it is good  bigger then mine.




 Maybe they cap it at .15 on the top end  works for me


actually your number range is better as it is .06 to .15

I have the solar array low cost power which allows for me to push the clock to  .13 - .15 since the power is cheap.

Vcore of .3V to .8V would be better, IMHO, spawning efficiencies of ~.06W/GH/s and ~.15W/GH/s respectively.
Guestimates per the vid's

the videos on youtube show a fine chip.

If sidehack builds us a piece of gear that volts down to .07 and up to .12  it will be very nice

AFIK the chip is a fact. In some posts Punin wrote about  eng samples and the video part 1,2,3 in youtube are showing this.
But... when production run will be available and if they are going to sell small quantities or samples is another question .
I think that it is not only up to Punin and big USD will talk

So that's like 5 and two thirds of a container

To be fair not the most ridiculous of their claims though

I have 2 other people that are actually communicating with me and I will have the chips when they are released. 

Well right now Kilo is pretty much the designated agent for getting chips. My conversation with Punin got as far as giving him some info to make out and send me an NDA around the end of January (which I never received) and then about two weeks later he dropped a line mostly to let me know he'd posted the 28nm info stuff. That's pretty much it.

Keep hoping!

I hope so too buddy

Well lets hope that you guys get chips soon.  my solar panel array wants some bitfuries!

@ hedgy73

 I am sure Punin will sell sidehack some chips.