Topic: Bitfury: "16nm... sales to public start shortly" - page 33. (Read 108494 times)
Just tossing this rather interesting idea out there for general cogitation.... http://www.ecnmag.com/news/2015/10/liquid-cooling-moves-chip-denser-electronics
Any reacharounds are a bonus in my books
Hey man, accidents happen when you can't see what you're working on.
I'm 40+ too but still have troubles with the right target for sticking 
This is a Bitcoin mining board. Here people who never attempted to plug Type-A USB into Ethernet RJ-45 socket are considered computer experts.
Try it, they'll fit and won't break. I challenge you.
Try it, they'll fit and won't break. I challenge you.
I tried to stick it into everything when I was 16, now I am >40 (and married) and know exactly where it needs to go. No more sticking it in the wrong place
'Prolly should say that my extreme conservative approach to pcb layout comes from first making boards using tape on Mylar then cut Rubylith back in the 60's through pretty much the late 80's, virtually all analog from damn near DC through RF. You learn fast to be up on best-practices eg. Be Damn Careful and never assume - verify it.
When them durn newfangled PC's showed up and eventually combined with photoset machines for making the layout masks it made correcting problems/errors a lot less painful... Nowadays, just get a 4-board proto run from PcbExpress or whoever and not bad at all to make changes. But Lessons learned stick.
My favorite and now deceased columnist who perfectly mirrors my views on the electronics design process http://electronicdesign.com/author/bob-pease
Pay special attention on using sims like Spice. eg, how-to and how not-to.
His works should be mandatory coverage in any EE program.
This is only one side of the coin. But this coin has two sides. I believe that no amount of breadboarding or soldering would lead to things like https://en.wikipedia.org/wiki/Chua%27s_diode, https://en.wikipedia.org/wiki/Chua%27s_circuit and https://en.wikipedia.org/wiki/Memristor .When them durn newfangled PC's showed up and eventually combined with photoset machines for making the layout masks it made correcting problems/errors a lot less painful... Nowadays, just get a 4-board proto run from PcbExpress or whoever and not bad at all to make changes. But Lessons learned stick.
My favorite and now deceased columnist who perfectly mirrors my views on the electronics design process http://electronicdesign.com/author/bob-pease
Pay special attention on using sims like Spice. eg, how-to and how not-to.
His works should be mandatory coverage in any EE program.
Quote from: https://en.wikipedia.org/wiki/Leon_O._Chua
He is also the inventor and namesake of Chua's circuit one of the first and most widely known circuits to exhibit chaotic behavior, and was the first to conceive the theories behind, and postulate the existence of, the memristor. Twenty-seven years after he predicted its existence, a working solid-state memristor was created by a team led by R. Stanley Williams at Hewlett Packard.
But lets be realistic. This is a Bitcoin mining board. Here people who never attempted to plug Type-A USB into Ethernet RJ-45 socket are considered computer experts.
Try it, they'll fit and won't break. I challenge you.
Pease's topic http://electronicdesign.com/analog/what-s-all-spicey-stuff-anyhow-part-25 emphasizes that tools are only as good as the (known or all too often assumed ) data and conditions fed in. They definitely have their need but: Ya know - GIGO.
Now is my (conservative) approach overkill? Well for Consumer grade electronics probably so.
On USB-A/RJ-45... or if
'Prolly should say that my extreme conservative approach to pcb layout comes from first making boards using tape on Mylar then cut Rubylith back in the 60's through pretty much the late 80's, virtually all analog from damn near DC through RF. You learn fast to be up on best-practices eg. Be Damn Careful and never assume - verify it.
When them durn newfangled PC's showed up and eventually combined with photoset machines for making the layout masks it made correcting problems/errors a lot less painful... Nowadays, just get a 4-board proto run from PcbExpress or whoever and not bad at all to make changes. But Lessons learned stick.
My favorite and now deceased columnist who perfectly mirrors my views on the electronics design process http://electronicdesign.com/author/bob-pease
Pay special attention on using sims like Spice. eg, how-to and how not-to.
His works should be mandatory coverage in any EE program.
This is only one side of the coin. But this coin has two sides. I believe that no amount of breadboarding or soldering would lead to things like https://en.wikipedia.org/wiki/Chua%27s_diode, https://en.wikipedia.org/wiki/Chua%27s_circuit and https://en.wikipedia.org/wiki/Memristor .When them durn newfangled PC's showed up and eventually combined with photoset machines for making the layout masks it made correcting problems/errors a lot less painful... Nowadays, just get a 4-board proto run from PcbExpress or whoever and not bad at all to make changes. But Lessons learned stick.
My favorite and now deceased columnist who perfectly mirrors my views on the electronics design process http://electronicdesign.com/author/bob-pease
Pay special attention on using sims like Spice. eg, how-to and how not-to.
His works should be mandatory coverage in any EE program.
Quote from: https://en.wikipedia.org/wiki/Leon_O._Chua
He is also the inventor and namesake of Chua's circuit one of the first and most widely known circuits to exhibit chaotic behavior, and was the first to conceive the theories behind, and postulate the existence of, the memristor. Twenty-seven years after he predicted its existence, a working solid-state memristor was created by a team led by R. Stanley Williams at Hewlett Packard.
But lets be realistic. This is a Bitcoin mining board. Here people who never attempted to plug Type-A USB into Ethernet RJ-45 socket are considered computer experts.
Try it, they'll fit and won't break. I challenge you.
'Prolly should say that my extreme conservative approach to pcb layout comes from first making boards using tape on Mylar then cut Rubylith back in the 60's through pretty much the late 80's, virtually all analog from damn near DC through RF. You learn fast to be up on best-practices eg. Be Damn Careful and never assume - verify it.
When them durn newfangled PC's showed up and eventually combined with photoset machines for making the layout masks it made correcting problems/errors a lot less painful... Nowadays, just get a 4-board proto run from PcbExpress or whoever and not bad at all to make changes. But Lessons learned stick.
My favorite and now deceased columnist who perfectly mirrors my views on the electronics design process http://electronicdesign.com/author/bob-pease
Pay special attention on using sims like Spice. eg, how-to and how not-to.
His works should be mandatory coverage in any EE program.
When them durn newfangled PC's showed up and eventually combined with photoset machines for making the layout masks it made correcting problems/errors a lot less painful... Nowadays, just get a 4-board proto run from PcbExpress or whoever and not bad at all to make changes. But Lessons learned stick.
My favorite and now deceased columnist who perfectly mirrors my views on the electronics design process http://electronicdesign.com/author/bob-pease
Pay special attention on using sims like Spice. eg, how-to and how not-to.
His works should be mandatory coverage in any EE program.
Yes if you see any "snake" type traces its because they are parallel IO traces to some other longer traces, so they need to make the traces the same lengths hence the snakes. If you check out your PC motherboard you'll see them all over the place on the PCIe and RAM lanes. When your talking about throughputs in the muti Gigabits/s even the speed of light works against you
This does not matter on anything bitcoin related though, since these are very dumb chips IO rates coming to/from them are in the order of sub 1Mb/s, since nothing larger than a couple hundred bytes is ever sent to the chips( and return IO is even less...just an 8 byte nonce return and maybe a few bytes of chip info data).
You completely forgot about SSN (Simultaneous Switching Noise). This does not matter on anything bitcoin related though, since these are very dumb chips IO rates coming to/from them are in the order of sub 1Mb/s, since nothing larger than a couple hundred bytes is ever sent to the chips( and return IO is even less...just an 8 byte nonce return and maybe a few bytes of chip info data).
"Low rates have higher probability of issues
While it might appear that the higher the signal frequency, the more prominent the PDN issue might be, this is not always the case. The increased signal frequency certainly does carry with it an increase in signal integrity concerns, but not necessarily for the PDN. "
If the lines are long I'd want to see guard traces between each of the address and data lines running together. Short lines, say just a couple inches should be good but if np to have them there - do it.
As for the PDN itself it is a matter of the buck regulators switching freq vs the low speed coms. A buck will typically run between 50-250kHz, switching spikes from low speed coms can easily fall into that range if not looked after.
Good part is that the lit on the BitFury website for the 16nm chip says that all the needed supply bypassing is already present inside of the chip package so hopefully that will never be an issue when using the BitFury chips
You completely forgot about SSN (Simultaneous Switching Noise).
The Enterpoint's Cairnsmore is the best example. It was designed by a professional FPGA board designer, yet it failed to properly distribute clock from single Spartan 3 array controller to the four Spartan 6 mining chip. The guy who finally developed a working bitstreams had to do a lot of trial & error before he managed to squeeze the competitive output from that board. The competing 1.15y board from ZTEX did not exhibit those problems.
Even a simple, but regular and symmetric multichip design can produce hard to suppress resonances.
I applaud sidehack & friends for being careful. If they don't already have access to the appropriate analog models and software it is a very good decision to produce small and conservative design at first.
Edit: Being conservative is especially important with the attitude towards the interator designers exhibited by Bitfury and especially punin in the nearby thread. I presume that Bitfury doesn't even have proper IBIS models that would facilitate high-performance board design.
The Enterpoint's Cairnsmore is the best example. It was designed by a professional FPGA board designer, yet it failed to properly distribute clock from single Spartan 3 array controller to the four Spartan 6 mining chip. The guy who finally developed a working bitstreams had to do a lot of trial & error before he managed to squeeze the competitive output from that board. The competing 1.15y board from ZTEX did not exhibit those problems.
Even a simple, but regular and symmetric multichip design can produce hard to suppress resonances.
I applaud sidehack & friends for being careful. If they don't already have access to the appropriate analog models and software it is a very good decision to produce small and conservative design at first.
Edit: Being conservative is especially important with the attitude towards the interator designers exhibited by Bitfury and especially punin in the nearby thread. I presume that Bitfury doesn't even have proper IBIS models that would facilitate high-performance board design.
Careful! You might be approached for a collaboration...
Yes if you see any "snake" type traces its because they are parallel IO traces to some other longer traces, so they need to make the traces the same lengths hence the snakes. If you check out your PC motherboard you'll see them all over the place on the PCIe and RAM lanes. When your talking about throughputs in the muti Gigabits/s even the speed of light works against you
This does not matter on anything bitcoin related though, since these are very dumb chips IO rates coming to/from them are in the order of sub 1Mb/s, since nothing larger than a couple hundred bytes is ever sent to the chips( and return IO is even less...just an 8 byte nonce return and maybe a few bytes of chip info data).
You completely forgot about SSN (Simultaneous Switching Noise). This does not matter on anything bitcoin related though, since these are very dumb chips IO rates coming to/from them are in the order of sub 1Mb/s, since nothing larger than a couple hundred bytes is ever sent to the chips( and return IO is even less...just an 8 byte nonce return and maybe a few bytes of chip info data).
The Enterpoint's Cairnsmore is the best example. It was designed by a professional FPGA board designer, yet it failed to properly distribute clock from the single Spartan 3 array controller to the four Spartan 6 mining chip. The guy who finally developed the working bitstreams had to do a lot of trial & error before he managed to squeeze a respectable output from that board. The competing 1.15y board from ZTEX did not exhibit those problems.
Even a simple, but regular and symmetric multichip design can produce hard to suppress resonances.
I applaud sidehack & friends for being careful. If they don't already have access to the appropriate analog models and software it is a very good decision to produce small and conservative design at first.
Edit: Being conservative is especially important with the attitude towards the integrator's designers exhibited by Bitfury and especially punin in the nearby thread. I presume that Bitfury doesn't even have proper IBIS models that would facilitate high-performance board design.
Edit2: grammar & spelling fixes
My guess is that the 'snakey' lines are parallel coms of some sort and the bendy bits are to make sure the traces are the same length so signal propagation times are the same on all lines. Also note the lack of 90-deg corners aside from in the bendy bits. With 90-deg corners a trace is wider across the diagonal of the corner and that creates an impedance disruption in the transmission line at those points.
Yes if you see any "snake" type traces its because they are parallel IO traces to some other longer traces, so they need to make the traces the same lengths hence the snakes. If you check out your PC motherboard you'll see them all over the place on the PCIe and RAM lanes. When your talking about throughputs in the muti Gigabits/s even the speed of light works against you
This does not matter on anything bitcoin related though, since these are very dumb chips IO rates coming to/from them are in the order of sub 1Mb/s, since nothing larger than a couple hundred bytes is ever sent to the chips( and return IO is even less...just an 8 byte nonce return and maybe a few bytes of chip info data).
Great resources
But I actually do not think the sha 256 miner signalling is so sensitive.
From my experience just following the general PCB signalling rules is ok
But I actually do not think the sha 256 miner signalling is so sensitive.
From my experience just following the general PCB signalling rules is ok
Software no but I'll see what links to design articles re high-speed design and PDN considerations to watch for I can pull off of my computer at work manyana..
My guess is that the 'snakey' lines are parallel coms of some sort and the bendy bits are to make sure the traces are the same length so signal propagation times are the same on all lines. Also note the lack of 90-deg corners aside from in the bendy bits. With 90-deg corners a trace is wider across the diagonal of the corner and that creates an impedance disruption in the transmission line at those points.
EDIT: As promised
Damn good one on PCB routing and how it has changed http://electronicdesign.com/what-s-difference-between/what-s-difference-pcb-routing-then-and-now
Reflections and transmission lines http://www.eetimes.com/document.asp?doc_id=1280937
On EMI in general http://www.eetimes.com/document.asp?doc_id=1280798
On PDN design considerations http://powerelectronics.com/power-electronics-systems/five-things-every-engineer-should-know-about-pdn
Buck converter design http://powerelectronics.com/dc-dc-converters/buck-converter-design-demystified
Another on EMI in general http://machinedesign.com/motion-control/eliminating-emi-motion-systems
As for articles on stripline layout tips.. most of what I know is from decades of reading on it/working with it.
My guess is that the 'snakey' lines are parallel coms of some sort and the bendy bits are to make sure the traces are the same length so signal propagation times are the same on all lines. Also note the lack of 90-deg corners aside from in the bendy bits. With 90-deg corners a trace is wider across the diagonal of the corner and that creates an impedance disruption in the transmission line at those points.
EDIT: As promised
Damn good one on PCB routing and how it has changed http://electronicdesign.com/what-s-difference-between/what-s-difference-pcb-routing-then-and-now
Reflections and transmission lines http://www.eetimes.com/document.asp?doc_id=1280937
On EMI in general http://www.eetimes.com/document.asp?doc_id=1280798
On PDN design considerations http://powerelectronics.com/power-electronics-systems/five-things-every-engineer-should-know-about-pdn
Buck converter design http://powerelectronics.com/dc-dc-converters/buck-converter-design-demystified
Another on EMI in general http://machinedesign.com/motion-control/eliminating-emi-motion-systems
As for articles on stripline layout tips.. most of what I know is from decades of reading on it/working with it.
Er, SideHack and I were just discussing them early this morning... Get out of our minds!!! 
the pic of the BitFury 48 chip board is pretty but considering all those traces are address and data coms lines that is just begging for trouble from crosstalk and depending on the actual speed the coms to each chip are, signal reflection. Problematic but usable with careful termination at both ends of the traces but shorter is better and easier to push to higher speeds.
Yeah, better be safe than sorry. To my eyes the board looks only mildly complicated with respect to transmission line problems.the pic of the BitFury 48 chip board is pretty but considering all those traces are address and data coms lines that is just begging for trouble from crosstalk and depending on the actual speed the coms to each chip are, signal reflection. Problematic but usable with careful termination at both ends of the traces but shorter is better and easier to push to higher speeds.
Compare it with a rather low-end FPGA kit adapter from Xilinx; look at the snaking traces between JX1 and JX2.
Can anybody here make an educated guess on how many revisions it took Bitfury to come up with their published design? It says "V3.1", what could that mean?
Is anyone here familiar with any commercial software for frequency-sensitive PCB design? I only used custom Fortran software. Bitfury himself posted some links years ago:
Edit:
http://home.educities.edu.tw/oldfriend/article/PI/Power_Plane_and_Decoupling_Optimization.pdf
http://home.educities.edu.tw/oldfriend/article/PI/PI%20and%20GND%20bounce%20sim.pdf
http://home.educities.edu.tw/oldfriend/Tutorials/Ansoft/Ansoft%20solution%20review.pdf
Edit2: At least those 3 links still used to work last year.
Edit3: Original bitfury's post from 2013:
https://bitcointalksearch.org/topic/m.2266329
I think it may be a bit more complicate then legos . I cannot say much about board design but would like to see what one of the guys like SideHack, NotFuzzyWarm etc say about the layout for the new chips, in regards to what appears to be extremely fine tracing routes and how to deal with the heat generated on an air cooled PCB
Er, SideHack and I were just discussing them early this morning... Get out of our minds!!! . I cannot say much about board design but would like to see what one of the guys like SideHack, NotFuzzyWarm etc say about the layout for the new chips, in regards to what appears to be extremely fine tracing routes and how to deal with the heat generated on an air cooled PCBthe pic of the BitFury 48 chip board is pretty but considering all those traces are address and data coms lines that is just begging for trouble from crosstalk and depending on the actual speed the coms to each chip are, signal reflection. Problematic but usable with careful termination at both ends of the traces but shorter is better and easier to push to higher speeds.
Think it is the pic of the 12v boards that looks far better. Coms multiplexers in the middle of chip groups keeping the data lines short to/from the ASICS.
As for air cooling.. so far pics from like the B-11 are showing just backside cooling. History repeating itself? We've see how long that lasts. Soon direct contact topside cooling of the chips is showing up.... Now if they can get away with it and the chips are actually only slightly warm to the touch with just cooling through a big thermal resistor called the circuit board -- then I'm impressed. Until then...
Oh, KNK: Thanks for repointing me to the PDF's (again) http://dl.bitfury.com/28nm/pdf/ dunna know how I missed them. Leave a lot out to really do it such as coms protocols but also answered a few question I had about the BitFury boards - mainly WTF was that big loop structure? Is RFID tag to identify boards in the tanks. or at any other stage when board ID is needed.
I think it may be a bit more complicate then legos . I cannot say much about board design but would like to see what one of the guys like SideHack, NotFuzzyWarm etc say about the layout for the new chips, in regards to what appears to be extremely fine tracing routes and how to deal with the heat generated on an air cooled PCB
. I cannot say much about board design but would like to see what one of the guys like SideHack, NotFuzzyWarm etc say about the layout for the new chips, in regards to what appears to be extremely fine tracing routes and how to deal with the heat generated on an air cooled PCB Avalon uses a third-party reseller (at least for orders outside China, not sure about inside) with a MOQ of 10 units. Not openly small-customer hostile, but not exactly friendly either.
I know the A2 is an Innosilicon chip, but is the Terminator an Innosilicon product or built by a third party? Also, pretty sure that's a scrypt miner so not bitcoin (just covering technicalities).
I know the A2 is an Innosilicon chip, but is the Terminator an Innosilicon product or built by a third party? Also, pretty sure that's a scrypt miner so not bitcoin (just covering technicalities).
The A2 Terminator and the Farm Boy were sold by Innosilicon, though some of the design of the Terminator may have originated from Lketc.
Yes, the A2 chip is Scrypt - but nobody specified "Bitcoin miners" in the "only Bifmain" statement I was responding to.
Based on hashrate the last couple days, it looks like Bitmain appears to be shipping SOMETHING. Might be someone else, but I've not seen any reports at all yet of B-Elevens from BW.com for sale yet, and Avalon isn't shipping enough units to affect the hashrate noticeably.
Hm. What are the chip pinouts, protocols, and voltages required to fire it? I may have just the board to put 8 of these chips on............
As far as I know BitFury has not even released said info for their 28nm chip. (If I'm wrong, someone please to point where it is...) Even as a preliminary-spec sure as hell aren't going to release info on the 16nm chip...For the 16 nm , they have docs and they provide it to 1M MOQ customers AFIK
And therein lies the problem.
a. How many chips does that buy and what is the delivery schedule?
That right there is main thing that matters to anyone considering designing/building a miner.
b. Very few if any in the Community here at least -note the big 'C' - have that kind of disposable coin to fill the MOQ. Those that do most likely will not run it as an eventual open-source venture.
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