Topic: Bitfury: "16nm... sales to public start shortly" - page 47. (Read 108551 times)

And please read again carefully:

According to TSMC’s Mark Liu, “As you can see in our 7-nanometer development schedule that probably will not using EUV. But we are planning to exercise EUV using the 7-nanometer technology and currently we are planning to use EUV at 5-nanometer. But of course it does depend certain development criteria, milestones to be reached. And it has a good benefit from our assessment on the 7 — on the 5-nanometer that reduce a lot of many masking layers and increase a lot of better control for the 5-nanometer.”

TSMC thinks that they can even handle 7nm without EUV!

In principle it sounds like you know what you are talking about. But in this case you should also know that GloFo and Samsung have an identical 14nm FinFET node (with identical litho tools).
This deal was made in 2014, because Samsung was looking for a second source and GloFo was struggling with its own 14nm development. Glofo licensed the Samsung technology and brought it up in its US fab (Fab 8 ).

And I'm also pretty sure that there is absolutely no EUV litho involved in the 14/16nm technologies. Just double patterning for the critical masks. (What do you think what I do day by day? )

And no fab would announce ready for volume production if they would only have 40% yield for a typical SoC product like the iPhone 6 processor, which is produced in millions since last year in both Samsungs’s 14nm and TSMCs 16nm FinFET technologies. Do you really think, that Apple would accept 40% yield?
On top of that the iPhone 6 processor is much more yield critical than a Bitcoin mining ASIC, because it includes MBits of SRAM and does not tolerate any logic fault.

Of course, TSMC/Samsung and Glofo have already EUV tools working in their fabs, but only because they are already developing 10/7/5 nm technologies and running first prototypes e.g. to bring up the SRAM yield, which is the first thing they do. The other stuff is easy afterwards.

I'm also not really sure, what you are trying to say.
Something like: "Don’t worry! Bitfury has a super chip, but they can't produce it in volume, because the yield is low and TSMC doesn't care about $10M … $20M revenue."?

No, the foundries *are* using EUV right now despite the problems. I've worked with the companies involved.

Yes until EUV became better last year they pushed double patterning with conventional light sources far beyond what was thought possible but in no way did it work well enough for what the semi biz calls high volume production. TSMC and GloFo both use 13.8nm light sources while Samsung uses 9.5nm light (which is why they are producing actual 14nm junction chips vs 16nm). The talk of pushing back to the 7 and 5nm nodes was referring to that EUV may be able to work there as well instead of hitting a wall at 10nm.

SRAM is only a killer because it is the prime candidate to pack more (junctions) into the smaller area making leakage and bit failure a thorny issue. Couple that with wanting to push hard for ever higher speeds and you have self made (by the industry) issues. For mining ASIC's, as you said they are more robust and if you have a few dead cores, oh well, still a good chip. What has really helped is that only the patterning for making the junctions needs to be done with EUV, by using 20nm features for the intermediate layers the rest of the chip can be built up using very mature processes.

Right, I forgot about that part. Thanks.

The 40% yield refers to number of good chips per wafer - not cores per chip. As to what is a good chip, it one that meets spec. Preferably with 100% cores active @ stated speed. From there they will start stepping down the grade hopefully mainly by speed capability instead of by dead cores.

FYI

http://www.extremetech.com/extreme/210427-tsmc-confirms-volume-shipments-of-16nm-pushes-euv-back-to-the-5nm-node

No, 16nm use the 20nm BEOL (metal stack), which means there is almost no shrink from 20nm to 16nm.
And there is a classical shrink of a factor of 2 from 28nm to 20nm, like moore's law told us for many years now.

Sorry, but the foundries still managed to get 14/16nm working without EUV. Currently they are thinking that they need EUV starting with 5nm.

Normally SRAM is killing the yield of new technologies, but there is no SRAM in a Bitcoin Mining ASIC. In general these mining ASICs are very resilient and can also live with some faults. So I#m pretty sure, that one can achieve allready very high yields with a robust design style.

It will pass inspection at a lower grade and will be sold for a lower price. But its ratio of hash speed per power used will still be better than the competition.

I am making one assumption that somebody's at Bitfury has at least one brain cell working and will include circuitry to disable clock distribution to non-working hashing engines. If they have more than two working brain cells together they will include a way to fuse-out power to the non-working engines and there won't be even leakage.

The other thing increasing yield in mining chips is that they are 100% self-love, they don't have to meet any external timing constrains. If the defect is wafer-global, like all transistors have 1/3 of the normal Fmax, the chip is still competitive in GH/J and can be sold at a different price point.

The biggest yield differentiator is that SHA-256 is self-testing and requires exactly zero functional testing circuitry. The regular chips made for big-name customers most definitely require that at least the JTAG chain is operational on the whole surface of the chip, even if many functional units are defective and will be disabled when sold.

The NAND flash folks have this down to art. 90% chip not working? Sell it as a 10% capacity chip! Chip fails after 10 erases? Sell it to promotional merchandise vendors or as a one-time-programmable!

Bitfury folks seem to be rather intelligent. Their first chip included some analog self-test circuitry (ring oscillator?) that allowed for testing of the maximum speed that the chip wants to work (at particular temperature and supply voltage). It may not have worked as intended, but shows the grasp of technology.

The opposite can be said of Spoondoolies. They wasted chip estate for including some POST (power-on self test) circuitry. And then their software guy had to write code that re-enabled disabled engines which were failing only when cold and worked fine hot.

Edit: Remember the first Bitfury chip? They were 100% defective if one would try to apply traditional test methodologies. But somebody from Poland within first few days reverse-engineered the "defect" which turned out to be some sort of permutation of signals like (15-0) -> (1-16). They added appropriate compensating permutation in the driver and sold all of them.

Less than 10% operating correctly? So, about 820 cores instead of 8200? How's that pass inspection, or am I missing something? Admittedly I know nothing about the logic implementation of hash cores.

90% is a lowball estimate. The actual yield will be higher. The mining chips are so repetitive that they are commercially valuable even if less than 10% of it is operating correctly. It is the same story as with NAND flash memories.

 

For general info on the light source being used and its current status https://www.gigaphoton.com/en/news/3770 Note the date of the release.
They mention hitting a 24hr benchmark but that was an extended test run on a prototype and do not mention that it was test run only. That time between rebuild has not yet hit the foundries floors. btw: Gigaphoton and 1 other vendor makes the system which incorporates modules from other suppliers. Both use the same laser source and basic process to generate the EUV from their interaction with tin droplets.

One good sign of the various foundries confidence that the current tech used to generate EUV will be viable is that the sole supplier of the laser system used in it spent 70M euro's last June on an expansion to dedicated to make the lasers needed. http://optics.org/news/6/6/31. Has a good is basic description of how the EUV light is generated as well.

For info on TSMC's 16nm pr http://www.tsmc.com/english/dedicatedFoundry/technology/16nm.htm
Main consumers of TSMC's production http://www.tsmc.com/english/dedicatedFoundry/technology/application_specific_platform_solutions.htm Note that boutique ASIC's (eg for miners) don't even make the list unless maybe they fall under Power IC.

From 6mo ago, a hint at one of the players that have been footing the bill to reach 16/14nm chips http://wccftech.com/tsmc-begins-volume-production-16nm-finfet-nvidia-pascal-gp100-gpu/ It is only due to folks like them that targeted mid-volume high-end commercial/consumer use pricing has become available. Also one guess what fruity company has bought up almost all the current 16nm production capability of TSMC leaving far less available for miners (so far).

One other bright light at the end of the tunnel: keep in mind what foundries like TSMC, GloFo, and Samsung (Intel and IBM don't count here) consider when talking production volumes. Those are the ONLY foundries able to produce high volumes of 16/14nm chips. Period. Talk several hundred million to around 3/4 billion or more chips per month and you have their rapt attention. They won't even talk to you about 'boutique'' runs of only a million or so per month. I can't see the combined demand from BitFury and Bitmain being more than around a few hundred million chips/mo at best once things are proven out. But, with the processes getting better, miner ASIC's are able to tag along in many of the production steps and that translates into a lot of available custom chips space per step. Hopefully by now BitFury is up to full wafer status (with the attendant ~40% yield per-wafer). With Bitmain probably not far but silently behind???

All that said and done, it will certainly be interesting to see how BitFury's chip comes out!

If going by area, wouldn't shrinking from 28nm to 16nm be a factor of 3 decrease?

90% yield?  
That is WAAAAAY off base. That yield is common for higher nodes like 28nm on up but currently 16/14nm production yields are around 40% good dies and lower. They only began to hit 40% late last year...

Now the foundries are of course trying to get better but the processes are still under development. Biggest issue is the EUV light source used for the photo lithography. That monstrosity is still pretty hairy to run and is in no way capable of running 24x7. Is more like 8-20hrs followed by around 6 hrs to a full day of cleaning/realignment/process verification before starting another run of chips.

very close

The (QFN?) package should be about $0.20 .
This means, if your assumption is right, they would spend about $2.80 for the pure die.

How much is a 16nm wafer? Maybe about $9k if they make a good deal with TSMC?

This would result in about 3200 good dies per wafer. Right?

70000 mm² per 300 mm wafer and assuming 90% yield a single die size would be about 20 mm² (4.5mm x 4.5mm), which would fit to the package size.

8162 rolled cores; 65 clock cycles per hash -> equals about 125 unrolled cores;

A single semi-custom (standard cell based) unrolled core has an area of about 0.3 mm² in 28nm.
Implemented based on unrolled cores in 28nm a chip with equivalent performance would have a size of about 37.5 mm².
Taking the area scaling of a factor of 2 from 28nm to 16nm into account, the unrolled semi-custom version of the chip would have 18.75 mm² in 16nm (but would be probably not that efficient).

So I have to agree, your estimation is feasible and should be close to reality.

Unless it's a really bad design this chip should cost them about $3 to make (packaged). That's assuming 5 million chip quantities or 500 PH. What will they sell it for? Much more than this, that's for sure but I'd guess they want to give buyers a hope that they can pay back their costs in about 6-9 months, so probably around $8 for volume buyers, $10.50 for the plebs.

So, what you guys mean to say is that these chips would cost $30 - $50 /Chip, am I right?


If I assume that the chips cost me $45/chip an I need to achieve a hashing power of 10.2Th/s on immersion cooling I would require 60 chips and these chips would cost me $2700 Whoa!! thats a staggering amount. Between I have my fingers crossed for the prices.

LOL ... I guess more the other way around when it is based on 28 nm ... divide by 28 and multiply by 16  = 17.41 USD 

But this calculation was good for 28nm chips, so, you need to divide this number by 16(nm) and multiply it by 28(nm).
End result would be $53.28