This would result in about 3200 good dies per wafer. Right?
70000 mm² per 300 mm wafer and assuming 90% yield a single die size would be about 20 mm² (4.5mm x 4.5mm), which would fit to the package size.
That is WAAAAAY off base. That yield is common for higher nodes like 28nm on up but currently 16/14nm production yields are around 40% good dies and lower. They only began to hit 40% late last year...
Now the foundries are of course trying to get better but the processes are still under development. Biggest issue is the EUV light source used for the photo lithography. That monstrosity is still pretty hairy to run and is in no way capable of running 24x7. Is more like 8-20hrs followed by around 6 hrs to a full day of cleaning/realignment/process verification before starting another run of chips.
Sorry, but the foundries still managed to get 14/16nm working without EUV. Currently they are thinking that they need EUV starting with 5nm.
Normally SRAM is killing the yield of new technologies, but there is no SRAM in a Bitcoin Mining ASIC. In general these mining ASICs are very resilient and can also live with some faults. So I#m pretty sure, that one can achieve allready very high yields with a robust design style.
Yes until EUV became better last year they pushed double patterning with conventional light sources far beyond what was thought possible but in no way did it work well enough for what the semi biz calls high volume production. TSMC and GloFo both use 13.8nm light sources while Samsung uses 9.5nm light (which is why they are producing actual 14nm junction chips vs 16nm). The talk of pushing back to the 7 and 5nm nodes was referring to that EUV may be able to work there as well instead of hitting a wall at 10nm.
SRAM is only a killer because it is the prime candidate to pack more (junctions) into the smaller area making leakage and bit failure a thorny issue. Couple that with wanting to push hard for ever higher speeds and you have self made (by the industry) issues. For mining ASIC's, as you said they are more robust and if you have a few dead cores, oh well, still a good chip. What has really helped is that only the patterning for making the junctions needs to be done with EUV, by using 20nm features for the intermediate layers the rest of the chip can be built up using very mature processes.