Topic: Swedish ASIC miner company kncminer.com - page 1822. (Read 3049501 times)

I should have put a smiley there. Since they might be defective and only suitable for a photo.



In the case of a miner the wasted PCB is marginal, but packaged defective chips would be more of a concern as well as the time it takes to produce the defective board. However, the redundancy might give them the revenue they want even if they are wasting money on faulty devices.

What do you mean "unless they just want devices for a photograph"?  You said testing only takes seconds, so how would it make a difference in terms of their being able to photograph them?

As far as the PCB is concerned, I don't even understand why you care. If a PCB costs $20 per module then it is literally like 1% of the cost. a 50% yeild would only increase costs by 1%.   A 91% yield would only increase costs by 0.1%.   The PCB is essentially just more packaging.

It's also possible they meant testing before packaging, or something like that.

That's what I've been saying the whole time. Chips are tested in the fab during production using supplied test vectors. I've described the procedure above.  The standard procedure is also to include scan insertion and generate test vectors for the tester.

But now you are providing some new information: That KnC will do testing when they scale up the production? This contradict with information given earlier.

But I don't understand why they would want to skip testing on this in the first batch? (unless they just want devices for a photograph)

When they assemble their first set of miners and it does not work they will not know if it's a problem with the fabrication of the particular chip and will have to spend more time debugging trying to figure out where the problem is (device production, functional errors, software problems, power issues, FPGA logic, etc). If the device passed the chip level test you have one less unknown factor.

Chip level testing takes seconds (in some cases even less), not weeks. At 50% yield the fab would have been concerned and started investigation and tuning their process and tooling. Without any vectors they will not know and just continue to ship fully packaged defective chips to KnC at full price. But hopefully the problem would be detected by some other fab customer. But it might be that they don't care about throwing away money and are happy with whatever they are making.

Give it a rest. You're blowing this up completely out of proportion from a throwaway remark made at an open day months ago. As I said earlier, testing is what the semiconductor industry does.  Yes, this can be skipped for the very first samples off the production line, but its not the norm for production parts and won't be the norm with KNC either. Not sure what your point about customer or 3rd party testing is about ... chip packaging and final test is subcontracted, the test equipment is already there. You may need a custom socket/interface card built, but there are also standard fixtures for all the common packages, which will be perfectly adequate for the majority of devices.

I asked knc support and they said it will start hashing 24 hours max after it left the factory.
Maybe they are not hosted in sweden?

Yes, but do the math: You have a bitcoin hashing chip that can do 100Gh/s.  Today that's about $110 a day. $780 a week. Even if you had a 50% yeild, why would it matter if you had to throw away a PCB for every single working chip if it meant getting your chips a week earlier?

What people are doing every day is this: The chips are tested on the wafer. Bad chips are marked with dye. If enough chips are bad even the whole wafer is thrown away to save time/money on further processing. Bad chips are not packaged in order not to waste time/money on the package/packaging. The good chips are packaged. A final test is run on the packaged chip. In the old days wire bonding could fail. Today the majority uses flip chip which is not that sensitive as the thin bonding wires, but packaging could change the characteristic of the device. Only good chips are shipped to the customer. The fab has advanced and expensive fixtures to attach to both the die and the BGA package and run the given test vectors. This is standard procedure in the semiconductor industry.

It's not common to skip this chip level test (like it's claimed that KnC does) and let the customer or some 3rd party test the chip using some expensive fixture or run tests on actual PCB for the purpose of testing the chip (of course you run a lot of test on the PCB to detect bad solder joints and other assembly problems).

By not creating test vectors and skipping chip level testing you're potentially paying for a wafer and packages for chips which might even have been thrown away under normal circumstances. Not only that, you are also throwing away PCB's and other components unless you spend even more money on unmounting/reballing the good devices on the PCB.

I think still jobs is laughing as what he achieved, gates will not be able to achieve in his life time...current apple market cap 456 billion , Microsoft 264 billion....Microsoft neither have that finesse nor vision that Apple had......    

In any case lets start another thread for this as this is suppose to be a KNC thread ..lol

Yeah... well who's laughing now

(oh, also: http://www.youtube.com/watch?v=njos57IJf-0)

Yup ...i actually saw that interview....Jobs more or less screwed gates ....it was funny ...

Heh, maybe so.  But the point is competitors are photographed together and at least pretending to get along. Josh talked a lot of smack about KnC, I doubt they actually like him.

Yeah, the body language is off the charts. Look at how they're leaning away from each other, and the smiles look sorta forced (pulled down at the bottom, too toothy).

Jobs has got the "ha ha I'm going to stab you in your sleep" look going on.

those are smiles of hatred lol

Huh, you mean like this?


People competing with eachother are friendly all the time.

I can only hope that is true. Customer service told me last month that upgrade option would last until the end of August, but it is the middle of August right now and they closed that option. So, they must be at least two weeks ahead of schedule towards shipping.

I'm thinking the boards will already have chips mounted on them, which would mean production shortly after... but that's just me. I'm actually expecting some really good news... like shipping beginning the first week of September, nice, low wattage specs, and "Considerable" Gh/s gains. They do indeed have a track record now concerning the underpromise/overdeliver statement, and I'm lovin' it.

Of course they do, that's why they take pictures together and circle jerk eachother. You think if they were true competitors they would be all purple nurple friendly with eachother?

Hi Apple, Hi Microsoft can we hold hands and kiss? Hey get Linux in here we love eachother so much.

It doesn't matter though one or two members of the cartel will think about themselves and their business and truly compete and undercut their prices.

Did you guys listen to the latest Lets Talk Bitcoin?  They talk about how the ASIC makers collude with one another like a cartel.

If sample boards comes out next week, then, does that mean they are ahead of schedule or behind schedule? What usually happens in the time line? where are we?