Topic: Swedish ASIC miner company kncminer.com - page 1821. (Read 3049501 times)

tomorrow

Anyone know when the chips finish fabrication or they get sample chips?

you sooooo want to be a part of the process but you aren't..   why?

change you life and chase your dreams man.. 

you mean like the warning 'this product was made in a facility that also processes peanuts..  be aware you allergic fools.'

so if a fab also made BFL stuff, there should be a warning label on the miner

ROTFLMAO.

How early in October do you think you could get a unit at this time? I am guessing that you would be cutting it close to November if you order now. Let's say you buy a Jupiter and get a October 25th date. You would never get ROI according to http://mining.thegenesisblock.com/

All the better though. It is honestly better for them to sell out closer to November and not have to pre-order so soon. It is better to get it delivered as soon as you order, so, with luck, they will never sell out of October, and I could order it in November and get it in November.

You realize that an extra month of mining is worth more than the price difference?

I'm still waiting for October to sell out, so I could buy a November unit at a cheaper price.

I was actually thinking of starting a hosting service in NorthWest USA if there was enough interest. Would be miner friendly. 200/month, with a 3 month commitment for jupiters, and 150 for saturns, 100 for mercury.
Hosting would be available shortly after knc products start shipping, and would be exclusive to knc customers.  But would need be up-front to make it happen. ATX's available separate, or send own.

The one I talked to, admittedly the top hoster in my area, wanted $330 / month, some $2,000 setup fee, and a 3 year commitment >_>

Of all of those, it's the 3-year commitment that's particularly unrealistic.

Has anyone found a Bitcoin friendly hosting company for these in the US at a reasonable price. I would like to see something around $150 per month for a Jupiter.

I don't think there is a stats page. But I could be wrong. Think you have to track it yourself?

I feel like nobody will successfully get a free unit. Just an excessive in futility.  Funny to watch though!

Does anyone know where you can view your reseller info? Like stats on links or number sold? I emailed them but they never replied back.

Thanks for the compliment.

Unfortunately sitting here in this thread and trying out to straighten out every bit of misinformation would be a full time job and a very boring one. So I was trying to come up with some sort of general help for the readers here. The advice of the type "get an EE degree" is completely impractical.

When "Who moved my cheese?" was published and became an instant hit I keept saying that the book is so exagerrated that it becomes an unintentional comedy. Now I know that this book was not an exagerration.

So my advice is go read that book. It is very short, a fast reader can read it while having a large coffe and a croissant in a bookstore. You can buy it or borrow from a library.

It is essentially a pop-psychology piece, but once you read it you'll understand that it is a perfect alegory for a person like kingcoin. For 10 to 20 years kingcoin knew where and how to get his cheese. First he had to slice it by hand; now he has an ATPG tool to slice it for him. But suddenly Bitcoin ASICs came and moved his cheese. That triggered a psychological defense mechanism and turned him to a concern troll.

Bitcoin had already moved the cheese for many professionals. It will move it for many others. So if you plan on being involved in Bitcoin go read that book. It will help you to recognize the people who suffer from the "moved-cheese syndrome" by the easily recognizable psychological symptoms.

It's not very different from a multicore CPU or FPGA in this respect. AMD did sell N-1 core CPU's at a reduced price. FPGA's are one of the most complex devices in therms of transistor count and low yield is a likely problem. Xilinx will sell defective devices to their customers at a discount (AKA EasyPath). All this due to running test vectors on the chip tester. In the Xilinx case the logistics is more complex as they have to match their customer design databases against the defect list to figure which customer can use it.

Chip testing in the fab and analysis of the output would allow binning and KnC would have the flexibility of either only paying for 100% functional devices, or get a discount on the on partially defective devices. Without fab based testing they would pay the same price for fully functional and defective devices. Offering a second on each device using this procedure is not economically pointless.

Also without fab based testing is difficult to prove that a problem is related to the the ASIC and not some problem in the other areas of the miner. It's kind of like checking the rental car for damage at the time of checkout rather than arguing at return time that the dent is not your fault.

Thank you. I love reading posts that inform!

They could be generating SVF files now while waiting for the masks to be produced. A second on the tester will not increase the time to market. The time it takes an experienced DFT engineer to run the test tools and formal checkers is in the area of hours. I would even do this for the single purpose of having a higher confidence in the chip which is mounted on the board for the initial bring-up. One valid time to marked argument could be that the process is so new that the tool and library support would have to be developed first.

Well, as I thought: Office Space 2 will have a character named Milton the test collator who will constantly mumble "scan insertion", "ATPG", etc.

But here's the usefull information for the future. Yield in semiconductor industry is defined as a percentage of the dies that are "good" as opposed to "faulty". The decision between good/bad is binary only when the die contains a single circuit. It obviously applies to a CPU or a similar chip, because such a device contains a JTAG chain that is essentially threading through the every flip/flop on the chip. So if a defect breaks the JTAG chain the die becomes untestable and it isn't even worth to package it.

In the Bitcoin mining ASIC realm currently only ASICminer and Avalon have a single-engine dies. So those are the only two vendors that could conceivably use "yield" as a single percentage value.

Every other Bitcoin mining vendor have multi-engine dies: BFL has 16, bitfury has 756. To make such a chip "fail" you'll have to either kill their control logic or kill all the engines. In all other cases the chip is neither "good" nor "bad", but has some "inbetween" value that is neither 0% nor 100%.

KnC went one step ahead and their die consists of 48 engines and 4 completely independent "control logic" and "power supply" circuits. To make such a chip "fail" you'll have to e.g. kill all 4 contol logic cicuits or 3 control circuts and all 12 engines in the quadrant with the working control logic. If you kill only 11 engines in the "good" quadrant your resulting chip is 2.08% "good" and still has more performace than the 100% "good" Avalon chip.

Semiconductor manufacturing plants are prepared to deal with both types of "yield": the binary "pass/fail" type and the contiguous "quality curve" type. The problem is that the "quality curve" testing is complex and expensive, and therefore used only for the analog or mixed-signal devices. The "pass/fail" test is indeed cheap and quick and it is used for the vast majority of digital devices. But the Bitcoin mining ASIC is a completely atypical digital device therefore applying even a very cheap pass/fail test to it is economically pointless.

I've typed all this because I hope this will be usefull for the readers not well-versed in the electroinic engineering. I don't hope to sway Milton the tester's kingcoin's opinion, but I presume that the concern trolls will like him will keep poping up on this forum for many months, until the ways to characterize yield and test Bitcoin ASIC will become a common knowledge and will move from this subforum to the mining software subforum.

I can't believe you are still talking about this. The whole reason they did this is time to market, and they said so several times . Also, each system will be tested before being delivered to the customers. So, let's fill a couple more pages with guesses and useless banter.

If the NRE is $1M and each chip is $200 (just guessing some numbers, add real numbers if you have them), and you get a couple thousand defective/reduced capacity devices this part is significant. But what is the reason for wasting this money by not providing test patterns and do testing in the fab?


That's my point and what I have argued the whole time. All they have to do is provide some  test vectors and run them on the chip tester. This is common practice and quick and pretty cheap (even though you pay for tester time). And then why not do it properly and do scan insertion and ATPG to cover the other parts which is pretty much standard procedure in the industry these days.

Is the word may in your sentence above an indication of that you think this is something they should do, or that you have heard somewhere that they might supply vectors and run test on the tester?

Keep in mind the vast majority of their costs are NRE costs, not the cost of the physical chips once produced.  A low yeild won't be a problem so long as they have enough to ship to their first customers.

Also, if the testing actually doesn't add delays they may still have it done. They don't need to do anything special in the chip design in order to test it if they have test sockets for it.  All they have to do is feed it some work and see if the hashes come out right. That's it.