Topic: And some more delays in BFL shipment plans / no shipment before 14th Jan 2013 - page 11. (Read 22705 times)
December 11, 2012, 02:56:51 PM
I'm unfamiliar with Nick or John and I'm trying to forget that any of the Vleisides could have access to other people's money. It's not what I would consider a family name in good standing.
December 11, 2012, 02:49:17 PM
Has anyone ever actually met any of these people? I know exactly one BFL reps full name, the rest are all first names or convicted felons that seemingly have no official capacity with the company. I'll reserve my worry about Jody & her family's well being when I'm convinced there is a BFL_Jody.
Since BFL_Josh is in tight with Neal Fletcher and Neal Fletcher is a known puppetmaster over at bullshido...well color me skeptical.
I am not even going to touch that topic.Since BFL_Josh is in tight with Neal Fletcher and Neal Fletcher is a known puppetmaster over at bullshido...well color me skeptical.
What concerns me is that I get the impression that Jody and Josh are not even in the same building most of the time. They talk as if they haven't seen each other in the workplace [in the same day].
Whats up with that?
Why is Jody talking about it like it's the first shes heard of it? Isn't she GM (General Manager) and don't they see each other all of the time? Or is she a stay at home CS type of thing? (Serious question)
why does she act like she just heard the latest word from the blog or a post?
It's possible Jody Drake works from her office at home in front of the picture window watching her chickens.
http://www.linkedin.com/pub/jody-drake/13/556/4ba
http://www.awakeningworld.com/about.html
John Mutrux uses the same studio/home: http://www.mutrux.com/
http://asmp.org/community/chapters/chapter_profile.php?id=13
Quote
Board Member
John Mutrux
5217 England
Merriam, KS 66203
(913) 722-4343 Work
(913) 982-6120 Cell
[email protected]
Vice President
Chris Vleisides
2507 Jefferson
Kansas City, MO 64108
(816) 421-1077 Work
[email protected]
Board Member
Nicholas Vedros Nick V (?) (EDIT: possibly wrong Nick--I was thinking of Nick W)
1510 Jarboe Street
Kansas City, MO 64108
(816) 471-5488 Work
(816) 471-2666 Fax
[email protected]
John Mutrux
5217 England
Merriam, KS 66203
(913) 722-4343 Work
(913) 982-6120 Cell
[email protected]
Vice President
Chris Vleisides
2507 Jefferson
Kansas City, MO 64108
(816) 421-1077 Work
[email protected]
Board Member
Nicholas Vedros Nick V (?) (EDIT: possibly wrong Nick--I was thinking of Nick W)
1510 Jarboe Street
Kansas City, MO 64108
(816) 471-5488 Work
(816) 471-2666 Fax
[email protected]
December 11, 2012, 02:10:07 PM
...well color me skeptical.
Have you ever NOT been skeptical of BFL?Yes actually. I placed an order with them on 10/5/2012(#10299). I then asked if I could make partial payment via BTC and the rest bank wire. On 10/8 I received a reply, but they declined. I then began to do more research on BFL and their competitors and chose to next order from BTCFPGA. I had no reason to be skeptical of BFL at that point aside from their poor performance with their FPGA product rollout, which they assured everyone would not be repeated.
December 11, 2012, 02:03:52 PM
See above.
December 11, 2012, 02:00:58 PM
Has anyone ever actually met any of these people? I know exactly one BFL reps full name, the rest are all first names or convicted felons that seemingly have no official capacity with the company. I'll reserve my worry about Jody & her family's well being when I'm convinced there is a BFL_Jody.
Since BFL_Josh is in tight with Neal Fletcher and Neal Fletcher is a known puppetmaster over at bullshido...well color me skeptical.
I am not even going to touch that topic.Since BFL_Josh is in tight with Neal Fletcher and Neal Fletcher is a known puppetmaster over at bullshido...well color me skeptical.
What concerns me is that I get the impression that Jody and Josh are not even in the same building most of the time. They talk as if they haven't seen each other in the workplace [in the same day].
Whats up with that?
Why is Jody talking about it like it's the first shes heard of it? Isn't she GM (General Manager) and don't they see each other all of the time? Or is she a stay at home CS type of thing? (Serious question)
why does she act like she just heard the latest word from the blog or a post?
December 11, 2012, 02:00:04 PM
...well color me skeptical.
Have you ever NOT been skeptical of BFL? December 11, 2012, 01:59:07 PM
Has anyone ever actually met any of these people? I know exactly one BFL reps full name, the rest are all first names or convicted felons that seemingly have no official capacity with the company. I'll reserve my worry about Jody & her family's well being when I'm convinced there is a BFL_Jody.
Since BFL_Josh is in tight with Neal Fletcher and Neal Fletcher is a known puppetmaster over at bullshido...well color me skeptical.
Since BFL_Josh is in tight with Neal Fletcher and Neal Fletcher is a known puppetmaster over at bullshido...well color me skeptical.
December 11, 2012, 01:52:50 PM
Wow, surprisingly flippant:
https://forums.butterflylabs.com/blogs/bfl_jody/55-so-we-get-have-holiday.html#comment389
https://forums.butterflylabs.com/blogs/bfl_jody/55-so-we-get-have-holiday.html#comment389
Shhh...they're trying not to be discouraged. It's very important that they maintain their enthusiasm while other people's money is lost.
Please don't forget that when they screw this up, Jody is out of a job.... and that is something I wish on no one
Though, don't think she is all that different than Inaba. Possibly a few shades better....cause Inaba is plain "Awesome".
That aside, I did tell the BFL rep he would need a prayer to make it passed the next delay. Apparently, now people are questioning the health of the company. And these are bigger players (10k plus).
https://forums.butterflylabs.com/bfl-forum-miscellaneous/521-ringfenced-pre-order-funds-financial-health-bfl.html
If I were them, I would keep a good eye on the aucions and trade forums on bitcointalk.org to take a sample of what is going down. There are people selling off rigs in droves. (bASIC as well).
And you know how I feel about selling off rigs. The way it was done was questionable. IMO
December 11, 2012, 01:49:37 PM
Wow, surprisingly flippant:
https://forums.butterflylabs.com/blogs/bfl_jody/55-so-we-get-have-holiday.html#comment389
https://forums.butterflylabs.com/blogs/bfl_jody/55-so-we-get-have-holiday.html#comment389
Shhh...they're trying not to be discouraged. It's very important that they maintain their enthusiasm while other people's money is lost.
Please don't forget that when they screw this up, Jody is out of a job.... and that is something I wish on no one
I doubt it, they've already screwed it up big time. Nasser is wrong every time he posts. Has Josh been right about anything at all? Neither of these "professionals" have been fired, and one of them attacks customers and potential customers constantly.
No if heads were going to roll, they would have, starting with their blatantly incompetent COO and engineer. Assuming of course these are two different people IRL.
I meant that if they end up with no chips or massive refund requests, the company is not going to survive....
December 11, 2012, 01:43:34 PM
Wow, surprisingly flippant:
https://forums.butterflylabs.com/blogs/bfl_jody/55-so-we-get-have-holiday.html#comment389
https://forums.butterflylabs.com/blogs/bfl_jody/55-so-we-get-have-holiday.html#comment389
Shhh...they're trying not to be discouraged. It's very important that they maintain their enthusiasm while other people's money is lost.
Please don't forget that when they screw this up, Jody is out of a job.... and that is something I wish on no one
I doubt it, they've already screwed it up big time. Nasser is wrong every time he posts. Has Josh been right about anything at all? Neither of these "professionals" have been fired, and one of them attacks customers and potential customers constantly.
No if heads were going to roll, they would have, starting with their blatantly incompetent COO and engineer. Assuming of course these are two different people IRL.
December 11, 2012, 01:38:04 PM
Gonna be hilarious when the next batch of chips arrives defective too.
Guess someone got salt in their silicon.
Guess someone got salt in their silicon.
December 11, 2012, 01:35:20 PM
Wow, surprisingly flippant:
https://forums.butterflylabs.com/blogs/bfl_jody/55-so-we-get-have-holiday.html#comment389
https://forums.butterflylabs.com/blogs/bfl_jody/55-so-we-get-have-holiday.html#comment389
Shhh...they're trying not to be discouraged. It's very important that they maintain their enthusiasm while other people's money is lost.
Please don't forget that when they screw this up, Jody is out of a job.... and that is something I wish on no one
December 11, 2012, 01:32:02 PM
Wow, surprisingly flippant:
https://forums.butterflylabs.com/blogs/bfl_jody/55-so-we-get-have-holiday.html#comment389
https://forums.butterflylabs.com/blogs/bfl_jody/55-so-we-get-have-holiday.html#comment389
Shhh...they're trying not to be discouraged. It's very important that they maintain their enthusiasm while other people's money is lost.
December 11, 2012, 01:29:38 PM
Shall I dig up the posts where I said the very same thing to BFL's COO and he suggested BFL could still ship in December of 2012? ...he also suggested, I was a stupid, idiotic liar, and a waste of human flesh, but that's not really relevant.
How about the email from a BFL CS rep posted to bitcointalk suggesting that BFL expects to ship late December or early January?
They're liars bud, they're not nearly ready to ship finished ASIC products and they know it.
I recall. I recall he said the same to me. How about the email from a BFL CS rep posted to bitcointalk suggesting that BFL expects to ship late December or early January?
They're liars bud, they're not nearly ready to ship finished ASIC products and they know it.
A pathological liar, IIRC. You were receiving Inaba's anger and hatred of his own shadow.
I hope they pay him well. He seemed like an honest man before he took the job at BFL.
December 11, 2012, 01:26:16 PM
Wow, surprisingly flippant:
https://forums.butterflylabs.com/blogs/bfl_jody/55-so-we-get-have-holiday.html#comment389
https://forums.butterflylabs.com/blogs/bfl_jody/55-so-we-get-have-holiday.html#comment389
December 11, 2012, 01:12:54 PM
Shall I dig up the posts where I said the very same thing to BFL's COO and he suggested BFL could still ship in December of 2012? ...he also suggested, I was a stupid, idiotic liar, and a waste of human flesh, but that's not really relevant. 
How about the email from a BFL CS rep posted to bitcointalk suggesting that BFL expects to ship late December or early January?
They're liars bud, they're not nearly ready to ship finished ASIC products and they know it.
I recall. I recall he said the same to me. How about the email from a BFL CS rep posted to bitcointalk suggesting that BFL expects to ship late December or early January?
They're liars bud, they're not nearly ready to ship finished ASIC products and they know it.
December 11, 2012, 01:09:32 PM
This (bolded above) is actually not true. Every time we have a new chip, we tell the fab to split the lot and hold some wafers at various stages of production. That way if the final product has a problem that can be fixed with one or two metal layers, we can make the change, the fab makes masks for only those layers, then the held wafers restart from that point and finish in less time than the whole process. We also sprinkle spare gates throughout the design so we can make metal changes to add gates if required for bug fixes.
Example: A 24 wafer lot. Hold 6 wafers at 1 week, 6 more wafers at 2 weeks, 6 more at 3 weeks; finished 6 wafers come out at 4 weeks. If the chips work as expected, we release all the wafers and the remaining 18 come out in groups of 6 wafers every week for 3 more weeks. If we have a problem that can be fixed in the top layers of the chips, we can make a mask change and have fixed wafers in a week. If the problem is near the bottom, we need 3 weeks for the fix. (Note: above is simplified to make the example clearer.)
We are in sub 30nm now and we take about 5 or 6 weeks for a "super hot lot" at TSMC. I assume older (larger) processes take less time. But 0.8 days? I find that impossible unless you are talking a top layer metal change for wafers that were held near the end of the process. I cannot believe any fab in the world can go from blank wafers to finished chips in less than a few days for more than a 2 or 3 metal layer process. Do you have a reference for the 0.8 days number? Until I'm proven ignorant, I'm calling BS.
Example: A 24 wafer lot. Hold 6 wafers at 1 week, 6 more wafers at 2 weeks, 6 more at 3 weeks; finished 6 wafers come out at 4 weeks. If the chips work as expected, we release all the wafers and the remaining 18 come out in groups of 6 wafers every week for 3 more weeks. If we have a problem that can be fixed in the top layers of the chips, we can make a mask change and have fixed wafers in a week. If the problem is near the bottom, we need 3 weeks for the fix. (Note: above is simplified to make the example clearer.)
We are in sub 30nm now and we take about 5 or 6 weeks for a "super hot lot" at TSMC. I assume older (larger) processes take less time. But 0.8 days? I find that impossible unless you are talking a top layer metal change for wafers that were held near the end of the process. I cannot believe any fab in the world can go from blank wafers to finished chips in less than a few days for more than a 2 or 3 metal layer process. Do you have a reference for the 0.8 days number? Until I'm proven ignorant, I'm calling BS.
Missed a word there, 0.8 day per layer. I am not saying you can finish the whole chip in 0.8 days, for example our chip has 29 layers, as we released earlier this week in our development thread.
December 11, 2012, 01:06:37 PM
I also wonder which phase of production the fab is in. Mask set done? Wafers started?
Depending on the process and "hot lot" status, wafers typically take between 4 and 8 weeks.
Then there are extra days to (optionally) test the wafers, cut the wafers, package the parts, then test the final parts. Then ship and assemble (solder) them to the boards, then test the boards.
(Please NO jokes about 4 to 6 weeks. Above "4 to 8 weeks" is serious.)
If the wafers come out of the fab on Jan. 10, then I would guess first SC units will ship sometime between Jan. 21 and 31.
Depending on the process and "hot lot" status, wafers typically take between 4 and 8 weeks.
Then there are extra days to (optionally) test the wafers, cut the wafers, package the parts, then test the final parts. Then ship and assemble (solder) them to the boards, then test the boards.
(Please NO jokes about 4 to 6 weeks. Above "4 to 8 weeks" is serious.)
If the wafers come out of the fab on Jan. 10, then I would guess first SC units will ship sometime between Jan. 21 and 31.
I was wondering when people like you two are going to start posting. On a personal note, it is my job to view them as serious competitors, but I completely lost it when they mentioned the "chips" are on their way in 1-2 weeks but also said they are making adjustments.
fact: you can not make adjustments once the MASK is made. even if you were to run a gate/metal fix, you'd still have to run the whole process all over, which is a workflow of 2 month. This time is also completely not limited by man power, but limited to how fast the Fab can produce the layers, and this is not magic, it is mathematically calculable once you "tape-out", how fast you will get your chips back. all these are industry standard. TSMC, one of the big players in this field can produce a "super hot lot" in 0.8 days.
I didn't want to entering a fight of words originally, but I am going to say it now. they lied and I'm disappointed.
Example: A 24 wafer lot. Hold 6 wafers at 1 week, 6 more wafers at 2 weeks, 6 more at 3 weeks; finished 6 wafers come out at 4 weeks. If the chips work as expected, we release all the wafers and the remaining 18 come out in groups of 6 wafers every week for 3 more weeks. If we have a problem that can be fixed in the top layers of the chips, we can make a mask change and have fixed wafers in a week. If the problem is near the bottom, we need 3 weeks for the fix. (Note: above is simplified to make the example clearer.)
We are in sub 30nm now and we take about 5 or 6 weeks for a "super hot lot" at TSMC. I assume older (larger) processes take less time. But 0.8 days? I find that impossible unless you are talking a top layer metal change for wafers that were held near the end of the process. I cannot believe any fab in the world can go from blank wafers to finished chips in less than a few days for more than a 2 or 3 metal layer process. Do you have a reference for the 0.8 days number? Until I'm proven ignorant, I'm calling BS.
December 11, 2012, 12:45:44 PM
https://forums.butterflylabs.com/bfl-forum-miscellaneous/519-10-dec-2012-bfl-asic-update.html
But to cut to the chase the bottom line I read here is that you do not have the mask set done and you don't have clear understanding of the process that needs gone through to get the maskset done.
The maskset is the one huge expenditure that the ASIC foundry would be hesitant to spend unnecessarily. After the maskset is done, there is no reason not to let the train run its full course until the endstation. The costs involved are relatively minor compared to the huge upside if you happen to find yet another fault which you must correct for the next iteration.
You have clearly designed the chip too aggressively breaking some design rules that have now caused some speedbumps on the road. Professionals should have understood the design rules that need to be followed so that the speedbumps are either avoided or taken with full intent of doing so. If they come as a surprise you have at least failed to ask the right questions earlier.
Well these things you learn and next project you can do better.
What is the number one reason, why most companies are really afraid going to full-custom? I mean full-full-custom and not just standard-cell which sometimes somebody is also calling full-custom but clearly you are not doing so.
Well the reason is that ASIC projects have huge risks involved and going full custom further increases the risks exponentially. No matter where and what the risks are when they are finally realized, they still come back to the underlying rootcause of taking on the exponential risks when deciding to go full-custom. In your case I don't quite understand what was the upside gained from full-custom other than it has so expensive ring to it so it could win some preorders with that ring.
But to cut to the chase the bottom line I read here is that you do not have the mask set done and you don't have clear understanding of the process that needs gone through to get the maskset done.
The maskset is the one huge expenditure that the ASIC foundry would be hesitant to spend unnecessarily. After the maskset is done, there is no reason not to let the train run its full course until the endstation. The costs involved are relatively minor compared to the huge upside if you happen to find yet another fault which you must correct for the next iteration.
You have clearly designed the chip too aggressively breaking some design rules that have now caused some speedbumps on the road. Professionals should have understood the design rules that need to be followed so that the speedbumps are either avoided or taken with full intent of doing so. If they come as a surprise you have at least failed to ask the right questions earlier.
Well these things you learn and next project you can do better.
What is the number one reason, why most companies are really afraid going to full-custom? I mean full-full-custom and not just standard-cell which sometimes somebody is also calling full-custom but clearly you are not doing so.
Well the reason is that ASIC projects have huge risks involved and going full custom further increases the risks exponentially. No matter where and what the risks are when they are finally realized, they still come back to the underlying rootcause of taking on the exponential risks when deciding to go full-custom. In your case I don't quite understand what was the upside gained from full-custom other than it has so expensive ring to it so it could win some preorders with that ring.
I also wonder which phase of production the fab is in. Mask set done? Wafers started?
Depending on the process and "hot lot" status, wafers typically take between 4 and 8 weeks.
Then there are extra days to (optionally) test the wafers, cut the wafers, package the parts, then test the final parts. Then ship and assemble (solder) them to the boards, then test the boards.
(Please NO jokes about 4 to 6 weeks. Above "4 to 8 weeks" is serious.)
If the wafers come out of the fab on Jan. 10, then I would guess first SC units will ship sometime between Jan. 21 and 31.
I was wondering when people like you two are going to start posting. On a personal note, it is my job to view them as serious competitors, but I completely lost it when they mentioned the "chips" are on their way in 1-2 weeks but also said they are making adjustments.
fact: you can not make adjustments once the MASK is made. even if you were to run a gate/metal fix, you'd still have to run the whole process all over, which is a workflow of 2 month. This time is also completely not limited by man power, but limited to how fast the Fab can produce the layers, and this is not magic, it is mathematically calculable once you "tape-out", how fast you will get your chips back. all these are industry standard. TSMC, one of the big players in this field can produce a "super hot lot" in 0.8 days.
I didn't want to entering a fight of words originally, but I am going to say it now. they lied and I'm disappointed.
December 11, 2012, 12:24:53 PM
https://forums.butterflylabs.com/bfl-forum-miscellaneous/519-10-dec-2012-bfl-asic-update.html
But to cut to the chase the bottom line I read here is that you do not have the mask set done and you don't have clear understanding of the process that needs gone through to get the maskset done.
The maskset is the one huge expenditure that the ASIC foundry would be hesitant to spend unnecessarily. After the maskset is done, there is no reason not to let the train run its full course until the endstation. The costs involved are relatively minor compared to the huge upside if you happen to find yet another fault which you must correct for the next iteration.
You have clearly designed the chip too aggressively breaking some design rules that have now caused some speedbumps on the road. Professionals should have understood the design rules that need to be followed so that the speedbumps are either avoided or taken with full intent of doing so. If they come as a surprise you have at least failed to ask the right questions earlier.
Well these things you learn and next project you can do better.
What is the number one reason, why most companies are really afraid going to full-custom? I mean full-full-custom and not just standard-cell which sometimes somebody is also calling full-custom but clearly you are not doing so.
Well the reason is that ASIC projects have huge risks involved and going full custom further increases the risks exponentially. No matter where and what the risks are when they are finally realized, they still come back to the underlying rootcause of taking on the exponential risks when deciding to go full-custom. In your case I don't quite understand what was the upside gained from full-custom other than it has so expensive ring to it so it could win some preorders with that ring.
But to cut to the chase the bottom line I read here is that you do not have the mask set done and you don't have clear understanding of the process that needs gone through to get the maskset done.
The maskset is the one huge expenditure that the ASIC foundry would be hesitant to spend unnecessarily. After the maskset is done, there is no reason not to let the train run its full course until the endstation. The costs involved are relatively minor compared to the huge upside if you happen to find yet another fault which you must correct for the next iteration.
You have clearly designed the chip too aggressively breaking some design rules that have now caused some speedbumps on the road. Professionals should have understood the design rules that need to be followed so that the speedbumps are either avoided or taken with full intent of doing so. If they come as a surprise you have at least failed to ask the right questions earlier.
Well these things you learn and next project you can do better.
What is the number one reason, why most companies are really afraid going to full-custom? I mean full-full-custom and not just standard-cell which sometimes somebody is also calling full-custom but clearly you are not doing so.
Well the reason is that ASIC projects have huge risks involved and going full custom further increases the risks exponentially. No matter where and what the risks are when they are finally realized, they still come back to the underlying rootcause of taking on the exponential risks when deciding to go full-custom. In your case I don't quite understand what was the upside gained from full-custom other than it has so expensive ring to it so it could win some preorders with that ring.
I also wonder which phase of production the fab is in. Mask set done? Wafers started?
Depending on the process and "hot lot" status, wafers typically take between 4 and 8 weeks.
Then there are extra days to (optionally) test the wafers, cut the wafers, package the parts, then test the final parts. Then ship and assemble (solder) them to the boards, then test the boards.
(Please NO jokes about 4 to 6 weeks. Above "4 to 8 weeks" is serious.)
If the wafers come out of the fab on Jan. 10, then I would guess first SC units will ship sometime between Jan. 21 and 31.
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