[Archive] BFL trolling museum - page 36.

makomk

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Activity: 686

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Quote from: aTg on January 14, 2013, 03:39:18 AM

Will change the QFN package to BGA simply to transmit heat better?
The spartan6 have such plastic package and there is no problem, if they change to a BGA chip size should be larger and totally different PCB design starting from 0, I have not read anything about how long it will take to redesign the PCB or if that will fit inside its gleaming steel boxes sanding.

Yes there is, just trust me on this. Spartan-6 is a nightmare thermally speaking. The only reason everyone uses it for Bitcoin mining is because it's dirt-cheap compared to the FPGAs actually available in packages with decent thermals.

Also, unanticipated problem my ass. If you read the announcement it's clear they've known about this issue since well before they announced their heatsink design and casing for the Single and were just keeping quiet about it.

nathanrees19

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Activity: 196

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Quote from: BR0KK on January 14, 2013, 06:29:17 AM

Quote from: becoin on January 14, 2013, 06:25:42 AM

I guess there will be lots of refund requests in the following days once BFL customers read the new 'update'?

No there won't..... Most of them will still stick to BFL cause they believe (like really religious "batshitcrazy" people) that their holy savior ASIC will arrive soon. Even if there is another delay

Okay, what kind of delay are you expecting? Point to the part of their timeline where the failure will be.

Monster Tent

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How many days can you do chargebacks on credit cards for ? If they push back most delivery times past that they can take the money and customers cant do a chargeback.

nathanrees19

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Activity: 196

Merit: 100

Quote from: becoin on January 14, 2013, 06:25:42 AM

I guess there will be lots of refund requests in the following days once BFL customers read the new 'update'?

Why? They now have a published timeline to follow. If they fail to follow it, then the refunds will come in.

If anything, people will be more likely to order now that they have a better idea of what's happening.

greyhawk

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Activity: 952

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Quote from: becoin on January 14, 2013, 06:25:42 AM

I guess there will be lots of refund requests in the following days once BFL customers read the new 'update'?

Nope. They are happy as can be.

BR0KK

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Activity: 784

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Quote from: becoin on January 14, 2013, 06:25:42 AM

I guess there will be lots of refund requests in the following days once BFL customers read the new 'update'?

No there won't..... Most of them will still stick to BFL cause they believe (like really religious "batshitcrazy" people) that their holy savior ASIC will arrive soon. Even if there is another delay

Monster Tent

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Activity: 238

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Quote from: nathanrees19 on January 14, 2013, 06:24:21 AM

Quote from: Micon on January 14, 2013, 05:29:30 AM

started for a full investigation of BFL. Remember this is a representative of the company on the floor of CES 2013:

http://www.youtube.com/watch?v=UlWrmIqGs3Y&feature=youtu.be&t=2m36s

I think you should post this video more; not enough people know that you're in the habit of harassing company representatives to try and make them look bad on video.

BFL doesnt need anyone to make them look bad. They accomplish it by themselves.

becoin

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I guess there will be lots of refund requests in the following days once BFL customers read the new 'update'?

bitmar

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Activity: 182

Merit: 100

Quote from: Gyrsur on January 14, 2013, 06:07:16 AM

Quote from: bitmar on January 14, 2013, 05:30:04 AM

This update still does not explain the mass production of chips without a prototype and testing. The chances that these chips will work are the same as 100,000 lines of code written on paper by the programmer. They still do not know the exact parameters of chips. 0.8w per GH or 1.2w per GH - this is a great difference -> 50% !!!

Typical Phases of a Custom ASIC Design.
1. Feasibility Study
2. Design
3. Prototyping !!!!
4. Engineering Runs
5. Industrialization
6. Management of full IC Fabrication Process
7. Wide Selection of Processes and Technologies
8. Series Production
http://www.trias-mikro.de/html/prod_asic_overview_chipAlliance.html?1,1,0

BFL Phases:

1. Design
2. Series Production
3. Waiting for a miracle that the chips will work

I guess BFL did software simulations of the ASIC design and founded on these results the design was chosen for production without prototyping. Also the specs are founded on the software simulations I guess.

Software simulations of the Custom ASIC Huh

? LOL

nathanrees19

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Activity: 196

Merit: 100

Quote from: Micon on January 14, 2013, 05:29:30 AM

started for a full investigation of BFL. Remember this is a representative of the company on the floor of CES 2013:

http://www.youtube.com/watch?v=UlWrmIqGs3Y&feature=youtu.be&t=2m36s

I think you should post this video more; not enough people know that you're in the habit of harassing company representatives to try and make them look bad on video.

nathanrees19

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Activity: 196

Merit: 100

Quote from: Gyrsur on January 14, 2013, 06:07:16 AM

I guess BFL did software simulations of the ASIC design and founded on these results the design was chosen for production without prototyping. Also the specs are founded on the software simulations I guess.

It's possible that they had prototype chips in a different package, identified all the issues in them and rolled in the fixes with the package change.

nathanrees19

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Activity: 196

Merit: 100

Quote from: aTg on January 14, 2013, 03:39:18 AM

I have not read anything about how long it will take to redesign the PCB

With good engineers? A day. Throw in another day to get other engineers to review it. Add a few weeks to get them manufactured in whatever quantity. Since they would have made this design change at least a month ago (most likely more), they would have the PCBs by now.

PCBs are easymode next to ASICs.

Gyrsur

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Activity: 2856

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Bitcoin Legal Tender Countries: 2 of 206

Quote from: bitmar on January 14, 2013, 05:30:04 AM

This update still does not explain the mass production of chips without a prototype and testing. The chances that these chips will work are the same as 100,000 lines of code written on paper by the programmer. They still do not know the exact parameters of chips. 0.8w per GH or 1.2w per GH - this is a great difference -> 50% !!!

Typical Phases of a Custom ASIC Design.
1. Feasibility Study
2. Design
3. Prototyping !!!!
4. Engineering Runs
5. Industrialization
6. Management of full IC Fabrication Process
7. Wide Selection of Processes and Technologies
8. Series Production
http://www.trias-mikro.de/html/prod_asic_overview_chipAlliance.html?1,1,0

BFL Phases:

1. Design
2. Series Production
3. Waiting for a miracle that the chips will work

I guess BFL did software simulations of the ASIC design and founded on these results the design was chosen for production without prototyping. Also the specs are founded on the software simulations I guess.

smoothie

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Activity: 2492

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LEALANA Bitcoin Grim Reaper

Quote from: bitmar on January 14, 2013, 05:30:04 AM

This update still does not explain the mass production of chips without a prototype and testing. The chances that these chips will work are the same as 100,000 lines of code written on paper by the programmer. They still do not know the exact parameters of chips. 0.8w per GH or 1.2w per GH - this is a great difference -> 50% !!!

Typical Phases of a Custom ASIC Design.
1. Feasibility Study
2. Design
3. Prototyping !!!!
4. Engineering Runs
5. Industrialization
6. Management of full IC Fabrication Process
7. Wide Selection of Processes and Technologies
8. Series Production
http://www.trias-mikro.de/html/prod_asic_overview_chipAlliance.html?1,1,0

BFL Phases:

1. Design
2. Series Production
3. Waiting for a miracle that the chips will work

+1 without thorough testing and a prototype they are fucked if they think they can ship in Feb with no issues.

bitmar

full member

Activity: 182

Merit: 100

This update still does not explain the mass production of chips without a prototype and testing. The chances that these chips will work are the same as 100,000 lines of code written on paper by the programmer. They still do not know the exact parameters of chips. 0.8w per GH or 1.2w per GH - this is a great difference -> 50% !!!

Typical Phases of a Custom ASIC Design.
1. Feasibility Study
2. Design
3. Prototyping !!!!
4. Engineering Runs
5. Industrialization
6. Management of full IC Fabrication Process
7. Wide Selection of Processes and Technologies
8. Series Production
http://www.trias-mikro.de/html/prod_asic_overview_chipAlliance.html?1,1,0

BFL Phases:

1. Design
2. Series Production
3. Waiting for a miracle that the chips will work

Micon

legendary

Activity: 1232

Merit: 1014

FPV Drone Pilot

My BFL scam accusation thread:

https://bitcointalksearch.org/topic/m.1453090

started for a full investigation of BFL. Remember this is a representative of the company on the floor of CES 2013:

http://www.youtube.com/watch?v=UlWrmIqGs3Y&feature=youtu.be&t=2m36s

PuertoLibre

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Activity: 1890

Merit: 1003

Quote from: DobZombie on January 14, 2013, 04:15:10 AM

Quote from: Inaba on January 13, 2013, 08:37:51 PM

Quote from: PuertoLibre on January 13, 2013, 08:33:16 PM

https://forums.butterflylabs.com/bfl-forum-miscellaneous/690-13-jan-2013-asic-update-discussion-thread.html

An update that is...empty....

Just like your head.

lol!

You amuse easily, like a circus monkey.

Quote from: greyhawk on January 13, 2013, 07:11:26 AM

Turns out I must apologize. The Box of Fans isn't a Box of Fans at all as this new picture shows

It's a box of fans and space(rs).

aTg

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Activity: 1358

Merit: 1000

Quote from: ElectricMucus on January 14, 2013, 04:01:29 AM

Quote from: aTg on January 14, 2013, 03:39:18 AM

Will change the QFN package to BGA simply to transmit heat better?
The spartan6 have such plastic package and there is no problem, if they change to a BGA chip size should be larger and totally different PCB design starting from 0, I have not read anything about how long it will take to redesign the PCB or if that will fit inside its gleaming steel boxes sanding.
When you have so many delays and are desperate to introduce the team, not more logical to have some little problem of heat put to redesign everything from almost 0?
What I see is to announce that you can put a BGA, and finally solder a latest generation FPGA with sanded surface ...

Yes, however that even a last gen FPGA meets the performance requirements even by a magnitude is unrealistic.

Or it could in fact turn out to be consistent with a commonly sold structured ASIC like Altera Hardcopy & Co, what I mentioned all along, for which Josh countered "you know what we are using another package format, ha!"
Oh the "sidenote" that the performance/jule figures could be "a little off" is totally consistent with that too, just that if it turns out to be a structured asic it wouldn't just be a "little off".

If it weren't for the possibility of a total fuckup... oh well. Roll Eyes

Is that I assume from the beginning that it will be a structured asic ...
And they will not deliver 60 GH/s

DobZombie

hero member

Activity: 896

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Former curator of The Bitcoin Museum

Quote from: Inaba on January 13, 2013, 08:37:51 PM

Quote from: PuertoLibre on January 13, 2013, 08:33:16 PM

https://forums.butterflylabs.com/bfl-forum-miscellaneous/690-13-jan-2013-asic-update-discussion-thread.html

An update that is...empty....

Just like your head.

lol!

ElectricMucus

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Activity: 1666

Merit: 1057

Marketing manager - GO MP

Quote from: aTg on January 14, 2013, 03:39:18 AM

Will change the QFN package to BGA simply to transmit heat better?
The spartan6 have such plastic package and there is no problem, if they change to a BGA chip size should be larger and totally different PCB design starting from 0, I have not read anything about how long it will take to redesign the PCB or if that will fit inside its gleaming steel boxes sanding.
When you have so many delays and are desperate to introduce the team, not more logical to have some little problem of heat put to redesign everything from almost 0?
What I see is to announce that you can put a BGA, and finally solder a latest generation FPGA with sanded surface ...

Yes, however that even a last gen FPGA meets the performance requirements even by a magnitude is unrealistic.

Or it could in fact turn out to be consistent with a commonly sold structured ASIC like Altera Hardcopy & Co, what I mentioned all along, for which Josh countered "you know what we are using another package format, ha!"
Oh the "sidenote" that the performance/jule figures could be "a little off" is totally consistent with that too, just that if it turns out to be a structured asic it wouldn't just be a "little off".

If it weren't for the possibility of a total fuckup... oh well. Roll Eyes

Topic: [Archive] BFL trolling museum - page 36. (Read 69394 times)